Abstract: A linear attenuator (23) for applications such as front/rear audio fading receives an input current to be programmably attenuated according to an input code at an input node (29). A transistor (30) is connected between the input node (29) and inputs of current-steering cells (40, 50, 60), which pass portions of the input current to either an output node (32) or a second node in response to the input code. An amplifier (22) has a negative input terminal connected to the input node (29), a positive input terminal receiving a reference voltage, and an output terminal connected to a control electrode of the transistor (30). The operational amplifier (22) and the transistor (30) together regulate the voltage at the input node (29) to prevent distortion of the input current by making the input node (29) a virtual ground node. Thus the attenuator (23) avoids nonlinearities normally associated with transistors and the need to duplicate a digital-to-analog converter (DAC) (21) providing the input current.

Abstract: A combined multiplier/shifter (150) uses an existing high-speed multiplier to perform both multiplies and programmable left and right shifts without a dedicated high-speed shifter. A shift decoder (160) used in a shift mode provides first recoded signals according to a shift count and a shift direction. A recoder (161) recodes a multiplier input in a multiply mode to provide second recoded signals. A multiplier array (163) receives either a multiplicand or a shift operand at its multiplicand input, and uses either the first or second recoded signals selectively according to the mode. An output of the multiplier array (163) is either a product in the multiply mode or a first shift result in the shift mode. An output shifter (157) selectively adjusts the first shift result according to the shift direction to provide a second, final shift result.

Abstract: A parallel IIR filter (100) has low quantization effects and includes a multiplier (103) which multiplies a digital input signal by a constant, and an arbitrary number of biquad filters (104, 105). Outputs of the multiplier (103) and each biquad filter (104, 105) are summed together in a summing device (106) to provide an output signal of the IIR filter (100). The IIR filter (100) first expresses its transfer function as a cascade form transfer function, and then calculates the constant as a product of a constant term of each cascade form biquad term. The IIR filter (100) partially decomposes the cascade form transfer function to provide first order terms, and calculates numerator coefficients of the first-order terms. Pairs of decomposed terms are recombined to provide a parallel form transfer function, from which parallel form coefficients are taken and applied to the biquad filters (104, 105).

Abstract: An integrated circuit (40) has a low-power mode in which at least one switched inverter stage (60) of a clock amplifier (41) is disabled in response to a stop signal. The stop signal indicates that the integrated circuit (40) is in low-power mode. In one embodiment, each switched inverter stage is a complementary metal-oxide-semiconductor (CMOS) switched inverter (60), in which an additional P-channel transistor (61) is connected between the source of an inverter P-channel transistor (62) and a positive power supply voltage terminal, and in which an additional N-channel transistor (64) is connected between a source of an inverter N-channel transistor (63) and a negative power supply voltage terminal. A non-switched inverter stage (52) remains active during low-power mode to maintain a DC value of a clock input signal near a switchpoint of the clock amplifier (41).

Abstract: A pulse width modulator (PWM) (20) receives a two's complement input number and separates a sign bit from remaining less significant bits. The PWM converts these bits into an unsigned number in dependence on the sign bit. A comparator (41) provides a compare output signal in response to an output of a counter (30) equaling the unsigned number. An output circuit (25) provides first and second pulse width modulated signals for a length of time determined by the output of the comparator (41) in dependence on whether the sign bit indicates a positive or negative sign. In one embodiment, the PWM (20) converts a negative two's complement number to the unsigned number by one's complementing the least significant bits, and the output circuit (25) keeps the second pulse width modulated signal active for one additional clock cycle to fully convert to two's complement form, without the need for a carry operation.

Abstract: A single-chip microcontroller (30) includes a central processing unit (CPU) (31) and several memory-mapped peripherals (32, 33, 34, 35) connected to internal address (37) and data (38) buses. The microcontroller (30) includes a test port (40) for receiving test data and providing the test data to the address (37) and data (38) buses to access the memory-mapped peripherals (32, 33, 34, 35) directly. The microcontroller (30) thus allows testing of the memory-mapped peripherals (32, 33, 34, 35) without CPU overhead, significantly reducing test time. The test port (40) includes a shift register (44) which selectively updates address high, address low, and data fields using the test data so that a field need not be re-entered if it doesn't change between test cycles. The test port (40) receives the test data and test control signals via signal lines shared with a general purpose input/output (GPIO) port (33) and requires only one independent control signal line.

Abstract: A voltage controlled oscillator (VCO) (23) includes a periodic signal generator (30) such as a comparator (42)followed by a latch (43), and a logic gate such as a NAND gate (31) connected to the output of the latch (43) to adjust for asymmetries in the output signals from the latch (43). In one embodiment, the NAND gate (31) includes two pullup transistors (80, 81) receiving first and second output signals from the latch and connected between a first power supply voltage terminal and an output node (86). Two switching branches (82, 83 and 84, 85) each including two transistors are connected between the output node (86) and a second power supply voltage terminal. The order of the input signals received by the two transistors is reversed between the two switching branches (82, 83 and 84, 85) to compensate for any duty cycle asymmetries. A frequency divider (32) divides the output of the NAND gate (31) to complete the duty cycle adjustment.

Abstract: A signed arithmetic data processing system (20) detects a multiply (MUL) or a multiply-and-accumulate (MAC) instruction in which a multiplier and a multiplicand each assume their respective maximum negative values. If one or both of the operands is not equal to its maximum negative value, the multiplication proceeds normally, such as in a modified Booth's multiplier/MAC (33). However, if both operands are equal to their respective maximum negative values, the data processing system (20) substitutes a maximum positive constant for the output of the multiplier/MAC (33). This substitution allows the result to be expressed with one fewer bits. The resulting error is very small and becomes insignificant in most digital signal processing algorithms, especially those based on fractional, saturation arithmetic. Alternatively, an extra bit of precision may be achieved for a given hardware size.

Abstract: A high-speed barrel shifter (20) includes a shifter array (25) having a matrix of transistors (40) located at intersections of rows and columns of the matrix (40). The rows and columns alternately function as source and destination terminals. A fill portion (48) fills either a predetermined value or a data-dependent value such as a sign bit into vacated bit positions along rows in a bottom left portion (42). Thus the barrel shifter (20) can perform a data-dependent fill instruction within the shifter array (25) and avoids extra clock cycles associated with post-array processing. In one embodiment, an isolation portion (44, 45) separates a top right portion (41) of the matrix (40) from the bottom left portion (42) along a diagonal (43). The isolation portion (44, 45) isolates transistors in the bottom left portion (42), which are associated with rotates and fills, from transistors in the top right portion (41), which are associated with shifts, according to the direction of the shift.

Abstract: An integrated circuit (20) configures the active level of an input, output, or input/output pin by sensing a logic state on the pin's bonding pad (21) at the inactivation of a reset signal, such as a power-on reset signal. The integrated circuit (20) selects a true or complement signal to provide to or from an internal circuit (25). The voltage level on the pin is latched on the active-to-inactive transition of the power-on reset signal. Thus, the use of proper board-level termination resistors (70, 71) programs the pins to the desired active logic level without the need for additional logic circuitry or a dedicated device pin.

Abstract: A filter (62) receives an input current signal and provides a filtered output signal in response. The filter (62) presents an extremely low-impedance input node (72) to the source of the input current signal, such as a current digital-to-analog converter (DAC) (62), thus avoiding modulating the input current signal. The filter (62) includes a virtual ground circuit (70) connected to the input node (72) followed by a filter (80) such as a biquad filter. The virtual ground circuit (70) has a high-gain cascoded loop to provide an intermediate current at a high-impedance output terminal (82), which is connected to an input terminal of the filter (80). The virtual ground circuit (70) is implemented without operational amplifiers and resistors, thus providing high linearity without a large amount of integrated circuit area.

Abstract: The characteristics of a room in which a speakerphone (20) is located are measured by determining a time between a test signal and its first attack, and a number of sample periods between the first attack and a time when the average power in the echo falls below a threshold. The first-attack time determines a pre-filter delay and the number of sample periods determines a tap length for an adaptive echo-canceling filter (62). In a teleconferencing environment, an annoying initialization sequence is avoided by initializing filter coefficients for each microphone (140), and saving the initial filter coefficients generated thereby in a corresponding nonvolatile memory (104). In response to an off-hook signal, the coefficients are retrieved from the nonvolatile memory (104). During operation, the coefficients are constantly updated. If another microphone (141) is enabled, the stored coefficients corresponding to that microphone (141) are dynamically substituted for the present coefficients.

Abstract: A dual tone detector (100) for a single dual tone, a dual tone multi-frequency (DTMF), or similar system processes an input signal through both bandpass (103) and band reject (104) tone detectors. If both the bandpass (103) and band reject (104) tone detectors detect a tone, then the dual tone detector (100) provides a tone detect output signal. If only the bandpass tone detector (103), which is susceptible to false tones, detects a tone, then a voice input signal is muted and the tone detector (100) activates the tone detect output signal only if both the bandpass (103) and band reject (104) tone detectors subsequently detect a tone. In one embodiment, a dual bandpass/band reject tone detector (120) processes the input signal through shared front-end band reject filters (121, 122), limiters (124), resonators (127, 128), and a processing section (130) in order to save circuit area. Limiter and peak detector functions are also implemented in shared circuitry to further reduce circuit area.

Abstract: A regulated charge pump (43) includes a charge pump core (114) having a charging capacitor (80). An output voltage on a first terminal (72) of the charging capacitor (80) is transferred to a holding capacitor (81). A second terminal (73) of the charging capacitor (80) is alternatively connected to positive and negative power supply voltage terminals in response to non-overlapping clock signals. The first terminal (72) of the charging capacitor (80) is connected through first (150) and second (151) transistors to the positive power supply voltage terminal. A proportional portion (112) provides a coarse regulation by biasing the first transistor (150) proportional to a comparison between a predetermined fraction of an output voltage and a reference voltage. An integrating portion (113) provides a precise regulation by biasing the second transistor (151) proportional to an integrated difference between the output voltage and a reference voltage.

Abstract: A receiver (20) digitally tunes a radio frequency (RF) signal at the same time that it mixes the RF signal to a frequency suitable for demodulation and channel separation. A clock frequency divider (35) receives a reference clock signal, and divides the reference clock signal to provide a divided signal at a predetermined frequency, such as 20 kHz for AM stereo. A clock frequency multiplier (36) receives the divided signal and a digital tuning input signal, and provides an analog tuning signal at a multiple of the divided signal as determined by the digital tuning input signal. An analog multiplier (31) then mixes the RF signal with the analog tuning signal. An analog-to-digital converter (ADC) (32) receives an output of the analog multiplier (31), and is clocked by the reference clock signal to eliminate any clock phase error. A digital demodulator (38) then demodulates and further processes an output of the ADC (32).

Abstract: An ADPCM transcoder (60) includes an integral tone generator (65) which inserts a linear tone signal, such as a conventional DTMF tone signal, into either the transmit or receive data stream, or both. A digital PCM input signal is first converted to a first linear signal. If tone generation is enabled for transmission, then the linear tone signal is substituted for or added to the first linear signal and provided to an ADPCM encoder (63), which provides an ADPCM output signal in response. An ADPCM decoder (66) receives an ADPCM input signal and provides a second linear input signal in response. If tone generation is enabled for reception, then the linear tone signal is substituted for or added to the second linear input signal, and converted to a digital PCM output signal. The ADPCM transcoder (60) may also be integrated with other components of a signal processing system.

Abstract: A high-speed adder using a varied carry scheme, such as one of the carry-lookahead (CLA) type (30), includes a plurality of adder groups (32-37) each receiving some bits of two input operands. The adder groups are not identical but instead each adder group reduces a delay which is critical to its order. A least significant adder group (32) reduces a delay from operand input to carry output. A most-significant group (37) reduces a delay from carry input to sum output. Intermediate groups (33-36) reduce a delay from carry input to carry output.

Abstract: A phase locked loop (PLL) (40) simultaneously has both relatively-low power consumption and relatively-low jitter on a clock output signal. The PLL (40) includes a phase detector (41) and a phase error accumulator (42) connected to the output of the phase detector (41). The phase error accumulator (42) samples an output of the phase detector (41) at a relatively-high clock rate, but accumulates these samples and provides an output thereof to a loop filter (43) at a relatively-low clock rate. Thus the PLL (40) captures short periods of phase delay to maintain low clock output signal jitter, while at the same time, however, the loop filter (43) need only adjust its output periodically, at the relatively-low rate, thereby saving power. The phase detector (41) detects a metastable condition on a phase detector latch (60) and resolves to an up pulse or a down pulse to further reduce clock output signal jitter.

Abstract: A charge-balanced switched-capacitor circuit (50, 61) includes two capacitors (53, 54/72, 73) which are equalized by being connected in parallel during a first time period. This equalization cancels any mismatch in either capacitor (53, 54/72, 73) which would tend to affect an associated common-mode voltage. During a second time period, the two capacitors (53, 54/72, 73) are connected in series between two signal lines (42, 43). In one embodiment, the switched-capacitor circuit (50) forms a common-mode feedback sensing circuit by providing a common-mode feedback voltage to a fully-differential amplifier (41) at a common interconnection point of the two capacitors (53, 54). This embodiment draws no DC current, and thus prevents harmonic distortion of an output signal on the two signal lines when using a slew-rate limited amplifier (41). In another embodiment, the switched-capacitor circuit (61) functions as an input sampler at an input of a switched-capacitor amplifier circuit (60).

Abstract: A sigma-delta modulator (50, 100) attenuates a frequency domain characteristic of a feedback signal to a first stage (60) of the modulator (50, 100) near f.sub.s /2, where f.sub.s is the modulator's (50, 100) clock frequency. The modulator (50, 100) thus virtually eliminates in-band tones which are characteristic of known sigma-delta modulators, without complex dithering schemes. In one embodiment, the sigma-delta modulator (50, 100) includes a two-tap finite impulse response (FIR) filter (80) within a feedback loop of the modulator (50, 100). The two-tap FIR filter (80) smoothes transitions at an output of a second stage (70) to provide the feedback signal to the first stage (60). This architecture is useful for either a digital-to-analog sigma-delta modulator (50) or an analog-to-digital sigma-delta modulator (100).