Patents Represented by Attorney, Agent or Law Firm Pedro P. Hernandez
  • Patent number: 6492847
    Abstract: A digital driver circuit with one or more CMOS inverters intended as input stages, whereby for the MOS FETs of the inverters the channel width/length (W/L) ratio increases from stage to stage. The digital driver circuit includes an intermediate stage with two further CMOS inverters, connected between a supply voltage Vcc and ground. The driver circuit also includes an output stage having two MOS FETs with the drain terminals of both the MOS FETs of the output stage connected both to each other and to the output of the circuit, the W/L ratio of both MOS FETs exceeding that of the MOS FETs of the intermediate stage. The switch-over of the two MOS FETs of the output stage, occurring with changes of the digital input signal at the input of the circuit, is offset in time with respect to each other, thereby reducing current peaks.
    Type: Grant
    Filed: October 12, 2000
    Date of Patent: December 10, 2002
    Assignee: Texas Instruments Deutschland GmbH
    Inventors: Laszlo Goetz, Stefan Reithmaier, Martin Rommel
  • Patent number: 6490329
    Abstract: An integrated circuit device including a FIFO and a clock generator having a pulse swallower. The pulse swallower eliminates pulses from a reference frequency signal, producing a primary digital transceiver clock signal having a frequency of chiprate(S)(n), which is used to clock a digital transceiver when the device is in a primary mode. A first clock divider divides the frequency of the primary digital transceiver clock signal to produce a FIFO output clock signal having a frequency of chiprate(S). The FIFO has a data bus input for coupling to a data output, for example from an analog transceiver. The FIFO also has an external clock input for coupling to a clock output, for example from the analog transceiver. The external clock signal clocks the data into the FIFO asynchronous with the primary digital transceiver clock signal at a frequency of chiprate(S). The internal clock signal clocks the data out of the FIFO, synchronous with the primary digital transceiver clock signal at a frequency of chiprate(S).
    Type: Grant
    Filed: July 12, 2001
    Date of Patent: December 3, 2002
    Assignees: Dot Wireless, Inc., VSLI Technology, Inc.
    Inventors: Tien Q. Nguyen, John G. McDonough, David (Daching) Chen, Howard (Hau) Thien Tran
  • Patent number: 6486704
    Abstract: A programmable burst FIFO buffer (100) allows for burst of data to be loaded into memory (106) without the device writing into the buffer having to check on every clock cycle as to whether the buffer is full or not. The buffer (100) is also programmable and allows for “N” words to be loaded with “N” being programmable in any given burst without having to check for a buffer full condition. The buffer (100) also avoids the glitches associated with other buffer designs due to the write and read clock being in different domains.
    Type: Grant
    Filed: June 19, 2001
    Date of Patent: November 26, 2002
    Assignee: Texas Instruments Incorporated
    Inventor: Alan S. Hearn
  • Patent number: 6483821
    Abstract: The present invention is an improved system and method for transmitting and receiving digital information over mobile communication channels. The present invention includes an enhanced channel estimator (34) which iteratively estimates channel amplitude and phase distortion from received pilot and data signal information at various time instants. The iterative channel estimation scheme of the present invention provides increased performance of the transceiver system which allows for efficiencies such as transmission of a minimal amount of pilot information and reduction in the transmitted power.
    Type: Grant
    Filed: April 19, 1999
    Date of Patent: November 19, 2002
    Assignee: Texas Instruments Incorporated
    Inventors: Anand G. Dabak, Srinath Hosur, Timothy Schmidl
  • Patent number: 6483141
    Abstract: In a DRAM with a COB (capacitor over bitline) structure where one side of the storage node is approximately equal to the diameter of the contact plug, when the mask is mis-positioned when the storage node is formed, to prevent the underlying oxide film from being exposed at the side surface of the contact hole and to prevent that underlying oxide film from being inadvertently etched during wet etching. Contact plug 7 is formed with oxide film 20 attached on nitride film 5, that acts as an etching stopper during wet etching. By doing this, contact plug 7 is formed projecting upward above underlying oxide film 4 and preferably projecting above nitride film 5. After storage node 10 is formed, when oxide films 8 and 20 are removed by wet etching, underlying oxide film 4 is not exposed at the side surface of contact hole 6 and inadvertent etching of it can be prevented.
    Type: Grant
    Filed: August 30, 1999
    Date of Patent: November 19, 2002
    Assignee: Texas Instruments Incorporated
    Inventor: Michiaki Sano
  • Patent number: 6480068
    Abstract: The present invention provides a hardware assisted automatic gain control (AGC) for a communication network. A dedicated hardware portion of the AGC, which works in cooperation with software implemented functionality (400), is included to detect saturation conditions in the internal nodes of the analog front end (200) in which a plurality of gain stages (PGA1, PGA2, PGA3) and filter stages (H1, H2, H3) are interleaved with inaccessible intermediate points. The saturation detection logic includes a comparator (21, 22, 23) and flip-flop (27, 28, 29) for each gain stage (PGA1, PGA2, PGA3) and can be integrated directly in the analog front end 200. The dedicated hardware can further be included in a codec of a modem in a digital subscriber line (DSL) system.
    Type: Grant
    Filed: September 28, 2001
    Date of Patent: November 12, 2002
    Assignee: Texas Instruments Incorporated
    Inventors: Fernando A. Mujica, Prakash Easwaran, Sandeep Kesrimal Oswal
  • Patent number: 6480475
    Abstract: Improved approaches to provide flexibility in setting user data rates and managing delay in data transmission systems using a superframe structure and Time Division Duplexing (TDD) are disclosed. These improved approaches operate to provide intelligent insertion of dummy words (bits or bites) into a data stream to be transmitted. By inserting the dummy words, the invention is able to render codewords, symbols and superframes independent from user data rates. As a result, a wide range of user data rates are available in data transmission systems using a superframe and TDD.
    Type: Grant
    Filed: September 14, 1998
    Date of Patent: November 12, 2002
    Assignee: Texas Instruments Incorporated
    Inventors: Cory S. Modlin, Eugene Yuk-Yin Tang, Po Tong, Jacky S. Chow
  • Patent number: 6476734
    Abstract: A method for prioritizing protection in the symbol mapping of selected information includes the steps of supplying information bits and overhead bits. Interleaving the information bits and overhead bits to supply a plurality of interleaved data blocks. And selectively mapping the plurality of interleaved data blocks into a modulation symbol.
    Type: Grant
    Filed: September 7, 2001
    Date of Patent: November 5, 2002
    Assignee: Texas Instruments Incorporated
    Inventors: Gibong Jeong, Edwin Park
  • Patent number: 6473438
    Abstract: A variety of bi-directional data transmission systems that facilitate communications between a plurality of remote units (15) and a central unit (10) using a frame based discrete multi-carrier transmission scheme are disclosed. In each of the systems, frames transmitted from the plurality of remote units (15) are synchronized at the central unit (10). A variety of novel modem arrangements and methods for coordinating communications between a plurality of remote units (15) and a central unit (10) to facilitate multi-point-to-point transmission are disclosed. The invention has application in a wide variety of data transmission schemes including Asymmetric Digital Subscriber Line systems that includes the transmission of signals over twisted pair, fiber and/or hybrid telephone lines, cable systems that includes the transmission of signals over a coaxial cable, and digital cellular television systems that include the transmission of radio signals.
    Type: Grant
    Filed: October 22, 1997
    Date of Patent: October 29, 2002
    Assignee: Amati Communications Corporation
    Inventors: John M. Cioffi, John Bingham, Krista S. Jacobsen
  • Patent number: 6456590
    Abstract: A virtual input queue 80 count frames of data arriving an input port zo in an Ethernet switch 10 using shared memory 50. The shared memory 50 is allocated among 1-N input ports based on either a static or dynamic memory scheme. The static scheme allocates the shared memory 50 evenly among the input ports 20 or based on the input port transmission rate. In the dynamic memory scheme, the range of a virtual input queue's occupancy is divided into an underload zone, a normal load zone and an overload zone. When the virtual input queue is in the underload zone, the input port is kept on and reserved a memory capacity equal to a low threshold. When a virtual input queue is in the normal load zone, the virtual on queue 80 is reserved an additional amount of memory and the link is kept on or is turned on whenever possible. The memory capacity not used or reserved by any input port operating in at least the underload zone and normal load zone is shared by the input ports operating in the overload zone.
    Type: Grant
    Filed: February 16, 1999
    Date of Patent: September 24, 2002
    Assignee: Texas Instruments Incorporated
    Inventors: Jing-Fei Ren, Randall J. Landry
  • Patent number: 6456650
    Abstract: In a splitterless Digital Subscriber Line (DSL) modem 30, a receiver architecture (100) that permits monitoring of harmonics within the upstream channel of a DSL connection. The receiver (100) can detect the harmonics by monitoring the harmonics in some empty tones or specified tones. A threshold can be set to differ the normal noise power and harmonics power in those empty or specified tones. When a POTS device (10) coupled to same wire line pair (20) as the DSL modem (30) goes off-hook, the DSL modem (30) can switch from the normal state to an off-hook state in which the harmonics are reduced to minimum by transmitting only the upper sub-band tones of the upstream transmission channel at reduced power levels.
    Type: Grant
    Filed: February 4, 1999
    Date of Patent: September 24, 2002
    Assignee: Texas Instruments Incorporated
    Inventors: Yaqi Cheng, Adam M. Chellali, Michael O. Polley
  • Patent number: 6456673
    Abstract: Disclosed are radio frequency (RF) interference cancellation techniques that effectively estimate RF interference to the data signals being received using a frequency domain model, and then remove the estimated RF interference from the received data signals. Improved techniques for digitally filtering multicarrier modulation samples to reduce sidelobe interference due to the RF interference are also disclosed.
    Type: Grant
    Filed: November 30, 1999
    Date of Patent: September 24, 2002
    Assignee: Amati Communications Corporation
    Inventors: Brian R. Wiese, John A. C. Bingham
  • Patent number: 6452310
    Abstract: A thin film resonator and method includes a first electrode (110) and a second electrode (112) substantially parallel to the first electrode (110). An intermediate layer (120) is disposed between and coupled to the first and second electrode (110, 112). The intermediate layer (120) includes a first piezoelectric layer (122), a second piezoelectric layer (124), and a spacer layer (130) disposed between the first and second piezoelectric layers (122, 124). The spacer layer (130) has an acoustic impedance substantially the same as the first and second piezoelectric layers (122, 124) and is formed of a disparate material.
    Type: Grant
    Filed: January 18, 2000
    Date of Patent: September 17, 2002
    Assignee: Texas Instruments Incorporated
    Inventor: Carl M. Panasik
  • Patent number: 6452959
    Abstract: A method of generating one or more pseudorandom noise (PN) sequences for use in spread spectrum communications includes the steps of providing data at an input of memory which stores bits associated with a pseudorandom noise (PN) sequence: changing the data; and for each of a plurality of changes of the data, providing a selected PN bit of the PN sequence at an output of the memory based on the data.
    Type: Grant
    Filed: May 28, 1999
    Date of Patent: September 17, 2002
    Assignees: Dot Wireless, Inc., VLSI Technology, Inc.
    Inventor: John G. McDonough
  • Patent number: 6449324
    Abstract: Disclosed are radio frequency (RF) interference cancellation techniques that effectively estimate RF interference to the data signals being received using a frequency domain model, and then remove the estimated RF interference from the received data signals. Improved techniques for digitally filtering multicarrier modulation samples to reduce sidelobe interference due to the RF interference are also disclosed.
    Type: Grant
    Filed: May 24, 2001
    Date of Patent: September 10, 2002
    Assignee: Texas Instruments Incorporated
    Inventors: Brian R. Wiese, John A. C. Bingham
  • Patent number: 6445319
    Abstract: An analog-to-digital converter (ADC) (12) having a nonlinear transfer function with a unique mapping. The ADC (12) is adapted to produce a digital output signal for a plurality of analog input signals, and a transfer function modifying circuit (14) is coupled to the ADC circuit (13). The transfer function modifying circuit (14) is adapted to modify the ADC circuit (13) transfer function (34) to have a unique mapping. The ADC (12) transfer function has multiple transfer function segments with varying slopes. Further disclosed is a method for designing an ADC (12) having a nonlinear transfer function, and a method for calibrating an ADC (12).
    Type: Grant
    Filed: May 10, 2000
    Date of Patent: September 3, 2002
    Assignee: Texas Instruments Incorporated
    Inventor: Alexander R. Bugeja
  • Patent number: 6441703
    Abstract: A radio frequency filter system includes a first acoustic resonator (54, 56) for a first frequency and a second acoustic resonator (54, 56) for a second frequency. An acoustic reflector array (102, 152, 202) is coupled to an electrode of the first acoustic resonator (54, 56) and to an electrode of the second acoustic resonator (54, 56). The acoustic reflector array (102, 152, 202) includes a plurality of reflector layers (112, 152, 210). A first reflector layer (112, 152, 210) is operable to reflect a signal at substantially the first frequency. A second reflector layer (112, 152, 210) is operable to reflect a signal at substantially the second frequency.
    Type: Grant
    Filed: January 18, 2000
    Date of Patent: August 27, 2002
    Assignee: Texas Instruments Incorporated
    Inventor: Carl M. Panasik
  • Patent number: 6441760
    Abstract: A digital to analog converter (40) includes a pulse width modulator (14) and a class-D amplifier (16). The class-D amplifier (16) includes a low pass filter (34). A differential signal is available from two nodes (outp, outm) on the amplifier. Common mode compensation circuitry (42) generates a compensation signal during periods where a PWM signal is not being generated to maintain a common mode average value of (Avdd +Avss)/2 from the nodes, without affecting the differential signal.
    Type: Grant
    Filed: March 30, 2001
    Date of Patent: August 27, 2002
    Assignee: Texas Instruments Incorporated
    Inventors: Xavier Albinet, Pascal Guigon
  • Patent number: 6438721
    Abstract: In systems requiring the alignment of two clock signals or the alignment of a clock signal to a serial data stream, a current mode interpolator is often used to position the output clock signal. Traditional scan tests using external pins of the device are inappropriate because of their timing penalty and other built in self tests are inappropriate because of a large area or circuit complexity penalty. Therefore, a built in self test has been developed that does not impact the normal performance of the device and requires minimal additional circuitry. In this method, a small digital state machine is utilized to force the digital control logic for the current mode interpolator such that a single bit current comparator is sufficient to detect defects in the digital control logic and the current mode interpolator.
    Type: Grant
    Filed: July 28, 1999
    Date of Patent: August 20, 2002
    Assignee: Texas Instruments Incorporated
    Inventor: Douglas Wente
  • Patent number: 6421796
    Abstract: A method and a system for performing memory-based convolutional interleaving are disclosed. According to the disclosed method, delay lines (DL) are paired with one another within rows of a memory, where the pairing is effected so that the sum of the delay of the paired delay lines is constant over the rows. Both in transmission and in receipt of the interleaved data packets, one or more data packets are read from the oldest location of one of the paired delay lines, with one or more data packets from a received vector being written into this delay line; this reading and writing is repeated for each of the rows of the memory, advancing in a first direction. The process of reading and writing is then repeated for the other delay line in each of the rows of the memory, advancing in the opposite direction. The pairing of the delay lines (DL) in each row of the memory permits efficient implementation of convolutional interleaving, with a minimum of overhead processing required.
    Type: Grant
    Filed: January 10, 2000
    Date of Patent: July 16, 2002
    Assignee: Texas Instruments Incorporated
    Inventor: Alan Gatherer