Abstract: A stack capacitor capable of obtaining high capacitance in a limited area, thereby improving the integration degree of a semiconductor memory device and a process for fabricating the same.

Abstract: A junction and modular optical sharing terminal assembly incorporates a vertically-extending frame having a plurality of frame plates vertically mounted thereon and a plurality of horizontally-extending, telescopic tray guides mounted on the frame plates and which are movable between a retracted position and a horizontally-extended position. Horizontal tray modules rest on the tray guides and are movable between a retracted position and a horizontally-extended position. The tray modules include warehousing, junction, and connector trays, each having identical perimeters and terminating at their sides with identical anchoring bands which removably rest on the tray guides, and each including a molded part at its front edge. A resilient trigger band is mounted on each of the anchoring bands, and interacts with the molded part and the tray guides to lock the tray modules in their extended and retracted positions. A housing encloses the frame, the frame plates, the tray guides, and the tray modules.

Abstract: A method for manufacturing a semiconductor device is disclosed in which an insulating film is formed on a semiconductor substrate, elements are formed on the insulating film, the first oxide film is formed on the surface of the insulating film in the elements using plasma-enhanced chemical vapor deposition, a second oxide film is formed on the surface of the first oxide film using atmospheric-pressure chemical vapor deposition, a third oxide film is formed on the surface of the second oxide film using plasma-enhanced chemical vapor deposition, and organic spin-on-glass film is formed on the surface of the third oxide film, and etched back is performed until the organic spin-on-glass film is removed.

Abstract: A method for fabricating a gate electrode structure of a semiconductor device includes the steps of forming a refractory metal layer of such as tungsten over a substrate, a nitride layer of such as tungsten nitride on the refractory metal layer, and a low resistance metal layer of such as gold (Au) on the nitride layer, and etching and removing the portions of the refractory metal layer and the nitride layer that are existing outside a predetermined region. In place of the refractory metal layer, the refractory metal compound layer may be used. The nitride layer is formed by introducing a nitrogen gas into a sputtering system where reactive sputtering is carried out. Without sacrificing the reliability of the gate or barrier characteristics, it is possible to reduce the number of process steps otherwise required.

Abstract: A combination of a lower thin film transistor formed on an insulating substrate and an upper thin film transistor laminated over the lower transistor has a lower channel formed in the lower transistor, an upper channel formed in the upper transistor, a lower gate electrode disposed under the lower channel, an intermediate gate electrode disposed between the lower channel and the upper channel, and an upper gate electrode disposed over the upper channel.

Abstract: Plastic substrates, such as but not limited to phenolic cellulosic composites such as those used in conventional toilet seats, are heated at a temperature and for a time sufficient to degas the substrate, and are then coated with a powder, and heated to cure the powder coating. In a preferred embodiment, a water-based electrically conductive coating is first applied to a phenolic cellulosic composite, and cured while the substrate is heated to degas the substrate sufficiently, such that a subsequently applied powder coating will not suffer from popping during curing. In a preferred embodiment, the part is coated at a temperature below the cure temperature of the coating composition.

Abstract: An outside-insulated electronic element of a chip type has a body including an electronic element and a plate electrode which extends from the body of the element and is bent along a side surface and a bottom surface of the body of the element. The body of the electronic element including the plate electrode has a trapezoidal shape or a bow or arcuate shape. In this way, the gaps between the electronic elements when placed in a disk package can be reduced to a minimum.

Abstract: A serial data transfer apparatus includes a time base counter that counts by a clock signal (CLK). The count value of the time base counter at the point of time when the reception of the serial data (R.times.D) is completed is written into the reception buffer together with the reception data. Accordingly, in the central processing unit, when the reception data (R.times.D) is to be processed, the time difference since the reception serial data (R.times.D) can be detected by reading out the count value of the time base counter written in the reception buffer and by reading out the count value of the time base counter at present from the time base counter. Accordingly, time management of the reception data can be performed.

Abstract: A machine tool comprises a spindle device carrying a tool element attached to the forward end of a rotor spindle drivingly rotatable as supported by a control-type magnetic bearing device, a working force calculating unit for calculating a working force acting on the tool element upon the tool element coming into contact with a workpiece based on exciting current of a magnetic bearing of the bearing device, and a discriminating unit for discerning whether the contact of the tool element with the workpiece is normal or abnormal based on variations in the working force.

Abstract: A storage electrode of a DRAM cell in a highly-integrated semiconductor device has, in order to secure the surface area thereof greater than that of a conventional tunnel-type storage electrode, an upper plate of storage electrode formed over a lower plate of storage electrode separated therefrom by a predetermined distance, while interposing bars of irregularly shapes formed of a conductive layer to electrically connect the upper and lower plates.

Abstract: The invention provides a method of fabricating a semiconductor device on an SOI substrate having a single crystal silicon substrate, a silicon dioxide film laid on top of the silicon substrate and a single crystal silicon layer laid on top of the silicon dioxide film. The method includes the steps of forming a single crystal silicon island composed of the single crystal silicon layer in a first region in which the semiconductor device is to be fabricated, and selectively forming a low temperature deposition silicon dioxide film in a second region in which the semiconductor device is not to be fabricated in the presence of photoresist, so that the low temperature deposition silicon dioxide film covers side surfaces of the silicon island. The second region turns into an isolation region for electrically separating adjacent semiconductor devices.

Abstract: A method of fabricating a semiconductor device incorporates the steps of forming in succession a gate insulting film, a polycrystalline silicon film and a first insulating film on a semiconductor substrate surface, and etching a portion of the first insulating film, the polycrystalline silicon film and the gate insulating film to expose the semiconductor substrate. The exposed semiconductor substrate is etched to form a trench. The trench is then buried by depositing a second insulating film and thereafter a third insulating film. The second and third insulating films are then etched with the third insulating film being etched at a higher rate than the second insulating film. The polycrystalline silicon film is used as a stopper to leave behind the second and third insulating films in the trench. A fourth insulating film is deposited, and then etched again using the polycrystalline silicon film as a stopper. The side walls of the trench are thus coated with the fourth insulating film.

Abstract: A reprogrammable programmable logic array comprising a first write module for inputting data to be written and data to be compared, an AND CAM cell array block for, in a write mode, sequentially storing the write data from the first write module and, in a match mode, comparing the comparison data from the first write module with its pre-stored data and generating match signals in accordance with the compared result, a first address module for, in the write mode, generating sequential addresses and supplying the generated sequential addresses to the AND CAM cell array block, a second write module for inputting data to be written in the write mode, an OR CAM cell array block for storing sequentially the write data from the second write module in the write mode and detecting its pre-stored data corresponding to the match signals from the AND CAM cell array block in the match mode, a second address module for, in the write mode, generating sequential addresses and supplying the generated sequential addresses to t

Abstract: A silicon substrate is partially removed for forming a movable center portion connected through torsional portions to a stationary portion, and current flows through a coil formed in the movable center portion so that a moving contact formed in the torsional portion comes into contact with a fixed point.

Abstract: The present invention relates to various yeast artificial chromosomes (YACs) which contain all or a portion of the human EDA gene for anhidrotic ectodermal dysplasia, probes specific for human EDA gene and methods of diagnosis of EDA gene-related disorders.

Abstract: In a semiconductor integrated circuit device including a step-down circuit for stepping down an external power supply voltage to obtain an internal power supply voltage, the external power supply voltage can be applied to an internal signal processing circuit using a conventional terminal.

Abstract: A graphics processing apparatus carries out an antialiasing for obtaining an output image having smooth edges, enabling a speedy computation of approximate shading area rates of pixels by making use of neither a subpixel dividing process nor a shading pixel counting process. The apparatus comprises a discriminating part for discriminating the presence of an end point pixel at an edge portion of an image defined by a vector data, a computing part for computing the number of edge pixels by extracting two integer parts a, b from x coordinate values Xa, Xb of two points where a scanline intersects the vector data, a setting part for setting a x coordinate value of the end point pixel to the Xb only when an end point pixel is found at the edge portion, an approximate point part for determining an approximate point value C' from a prescribed factor c.times.