Abstract: Techniques and systems for planning of wireless networks are described. A system according to an aspect of the present invention receives inputs describing traffic statistics for a wireless network and computes network specifications. The system uses the traffic statistics and network specifications as inputs to a computationally tractable model used to compute parameters for the user level performance of the wireless network. The model may suitably be a processor sharing queuing model. The model employed by the planning system allows analytical solution for the desired user level parameters, given the characteristics and conditions entered as inputs and the intended network layout characteristics. Once a set of user level performance parameters has been computed, the values of the parameters are examined to determine if they meet predetermined requirements, in an iterative process continuing until a set of specifications has been developed that produces parameters meeting the requirements.

Abstract: Techniques for performing the processing of blocks of video in multiple stages. Each stage is executed for blocks of data in the frame that need to go through that stage, based on the coding type, before moving to the next stage. This order of execution allows blocks of data to be processed in a nonsequential order, unless the blocks need to go through the same processing stages. Multiple processing elements (PEs) operating in SIMD mode executing the same task and operating on different blocks of data may be utilized, avoiding idle times for the PEs. In another aspect, inverse scan and dequantization operations for blocks of data are merged in a single procedure operating on multiple PEs operating in SIMD mode. This procedure makes efficient use of the multiple PEs and speeds up processing by combining two operations, inverse scan (reordering) and dequantization, which load the execution units differently.

Abstract: A scalable reconfigurable register file (SRRF) containing multiple register files, read and write multiplexer complexes, and a control unit operating in response to instructions is described. Multiple address configurations of the register files are supported by each instruction and different configurations are operable simultaneously during a single instruction execution. For example, with separate files of the size 32×32 supported configurations of 128×32 bit s, 64×64 bit s and 32×128 bit s can be in operation each cycle. Single width, double width, quad width operands are optimally supported without increasing the register file size and without increasing the number of register file read or write ports.