Abstract: A computer system is provided which has ECC, and which system has a first group of SIMMs having DRAMs thereon for storing data bits and a second group of SIMMs having DRAMs thereon for the storage of check bits. The system also has a memory controller which is programmed to operate at least about 10 nanoseconds slower than the DRAMs. During the write cycle, check bits are generated for and specific to each data byte, with the bits of the data byte being stored in the first group of SIMMs and the check bits stored in the second group of SIMMs. During the read cycle, new check bits are generated and compared with the stored check bits. Each single bit error is corrected and certain multiple bit errors are detected.

Abstract: Hardware logic within a host bridge that connects a system bus to a peripheral bus using PCI bus architecture or a peripheral bus that uses a bus architecture similar to PCI. The hardware optimizes the speed at which data transfers are accomplished between the buses while translating the data transfers between the different architectures of the two buses.