Abstract: A leaky bucket checker which combines synchronous updates with event driven asynchronous updates triggered by packet arrivals. A synchronous update is performed exactly as an event-driven update by assuming that a packet of length zero has arrived at the time of the update. These updates are performed in a round robin fashion on each connection. Therefore, assuming that one such update can be performed in each clock tick, the maximum bit representation of the last update time state variable can be limited to N bits for 2.sup.N total connections. Given the reduced processing and storage costs, a great number of network connections and leaky bucket checkers is possible.

Abstract: A data processing system includes a processor, a system memory, one or more input/output channel controllers (IOCC), and a system bus connecting the processor, the memory and the IOCCs together for communicating instructions, address and data between the various elements of a system. The IOCC includes a paged cache storage having a number of lines wherein each line of the page may be, for example, 32 bytes. Each page in the cache also has several attribute bits for that page including the so called WIM and attribute bits. The W bit is for controlling write through operations; the I bit controls cache inhibit; and the M bit controls memory coherency. Since the IOCC is unaware of these page table attribute bits for the cache lines being DMAed to system memory, IOCC must maintain memory consistency and cache coherency without sacrificing performance. For DMA write data to system memory, new cache attributes called global, cachable and demand based write through are created.

Abstract: Regulation of the output supply voltage to a load powered by a rechargeable battery of a portable apparatus, typically a telephone, is advantageously implemented by exploiting the switching STEP-DOWN REGULATOR of an in-built battery charger. The regulator circuit configures itself in function of the voltage level at the regulator input to retain an unmodified constant current and constant voltage battery charger function as long as a sufficiently high voltage source is connected to the input. Otherwise the battery voltage is applied to the input of the regulator and configuring means modify automatically the partition ratio of an output voltage sensing divider of the voltage-mode control loop of the charger, isolate the battery pole from the output and disable the current-mode control loop of the charger.

Abstract: In a data processing system employing a disk array, prediction of a possible failure of a disk drive initiates copying of the data away from the potentially failing disk drive to a spare disk drive before the failing drive actually fails. If the disk drive does fail before the copying of the contents to a spare disk drive is completed, rebuilding of the remaining contents within the failing disk drive is performed.

Abstract: A test link protocol which continuously monitors each link in a network to ensure that the link is correctly transmitting data. Each switch, or torus has at least one of two functional components: Send Test and Receive Test. The Send Test component monitors control codes at a torus link output. The Receive Test component monitors control codes at a torus link input. After a predetermined interval, the Send Test component makes a request to send a test.sub.-- link control code. The torus sends the test.sub.-- link code to the neighboring torus, where it is removed from the data stream and sent to that torus' Receive Test. The Receive Test then generates a response message and makes a request to send that message back to the originating torus. After receiving the message, the Send Test analyzes the message to determine whether the network link is working correctly. An error is also declared if the Send Test does not receive a reply within a predetermined interval.

Abstract: A data processing system includes a host processor, a number of peripheral devices, and one or more bridges which may connect between the host, peripheral devices and other hosts or peripheral devices such as in a network. Each bus to bus bridge connects between a primary bus and a secondary bus wherein for the purpose of clarity, the primary bus will be considered as the source for outbound transactions and the destination for inbound transactions and the secondary bus would be considered the destination for outbound transactions and the source for inbound transactions. Each bus to bus bridge includes an outbound data path, an inbound data path, and a control mechanism. The outbound data path includes a queued buffer for storing transactions in order of receipt from the primary bus where the requests in the queued buffer may be mixed as between read requests and write transactions, the outbound path also includes a number of parallel buffers for storing read reply data and address information.

Abstract: Discloses a device and a method for checking by means of a checker (100). the data incorporating check bits read into a memory stack. The device comprises a first counter (20), which is connected through logical gates (30a-d) with some of the memory input lines (25), and a second counter (80) between the checker (100) and the memory (50), which is connected through logical gates (70a-d) to the memory output lines (55) corresponding to the memory input lines (25) with the first (20) and the second (80). counters generating continuous binary values.

Abstract: In a system having producer and consumer processes, a producing process look ahead in its outgoing data stream to ensure that there is data available to consumers on all outgoing streams. The producer looks ahead by keeping a data array in its memory space with an entry for each connected consumer. When the outgoing data stream becomes blocked, the producer searches the array for empty connections. Then, the producer scans the outgoing data stream for messages to send over the empty connections and sends such messages. Periodically, the producer checks the original connection to see if the blocking condition has ended.

Abstract: Comparative circuits 10, 100 for comparing a first address comprising at least two bits to a second address comprising an equal number of corresponding bits as the first address to determine if the first address equals or does not equal the second address as disclosed. Comparative circuits 10, 100 include two bit to four bit encoders for encoding each two bits of the first address into a first four bit representation, wherein each bit has an on state and an off state and only one of the four bits is in the on state at one time, each two bits of the second address into a second four bit representation, wherein each bit corresponds to a bit from the first four bit representation. The four bit representations are then inputted into the remainder of the comparator circuits 10, 100.

Abstract: A domino logic circuit includes an evaluation circuit for receiving input signals and performing a logic operation on the input signals, a passgate circuit for controlling the transmission of signals to an output circuit and a feedback latch circuit for holding the output of the evaluation circuit for a predetermined portion of a clock cycle. The output circuit may also include a pair of control transistors to allow the output latching circuit to be turned off during the evaluate portion of the clock cycle thus improving the speed of the domino logic circuit. During the first half of the reset portion of each cycle, the output latching circuit is active and allows the circuit to retain its output state. During the time the passgates are turned off, the evaluate circuit is disconnected and may begin resetting. During the second half of the reset portion of the clocking signal, the passgates open, which allows the output stage to be reset.