Abstract: The invention relates to a method of measuring the contact angle of wetting liquids on a solid surface with which a high measuring accuracy and better reproduceability of the measurement results is achieved. The method resides in that a laser beam is directed onto the interface line between the liquid and the plane solid surface in such a manner that a first part of the laser beam is reflected by the solid surface and a second part by the liquid surface. The second partial beam is used as measuring beam by determining the angle (.delta.) made between the measuring beam and the solid surface, said angle being in a fixed geometrical relationship to the contact angle (r). The contact angles which can be determined very accurately with this measuring method provide information on wetting properties of materials, the exact knowledge of which is of great significance for example for semiconductor fabrication.

Abstract: A raised source/drain transistor is provided having thin sidewall spacing insulators (54) adjacent the transistor gate (48). A first sidewall spacer (64) is disposed adjacent thin sidewall spacing insulator (54) and raised source/drain region (60). A second sidewall spacer (66) is formed at the interface between field insulating region (44) and raised source/drain region (60).

Abstract: The disclosure relates to a method of forming samples of alloys of group II-VI compositions having minimum dislocations, comprising the steps of providing a sample of a group II-VI compound, providing an enclosed ampoule having the sample at one end portion thereof and a group II element of the compound at an end portion remote from the one end portion, heating the sample to a temperature in the range of 350 to the melting temperature of the compound for about one hour while maintaining the group II element at a temperature more than 200.degree. C. below the sample temperature, heating the group II element to a temperature from about 5.degree. to about 50.degree. C. below the temperature of the sample while maintaining the sample at a temperature in the range of 350.degree. to 650.degree. C. both of about 15 minutes to about 4 hours, and then stoichiometrically annealing the sample at a temperature below 325.degree. C.

Abstract: This is a method for fabricating integrated heterojunction bipolar transistors (HBTs) and heterojunction field effect transistors (HFETs) on a substrate. The method comprises: forming a subcollector layer 12 over the substrate 10; forming a collector layer 14 over the subcollector layer; forming a base layer 16 over the collector layer; etching the base layer to form one or more base pedestals 16 over a portion of the collector layer; forming a buffer region 18 in a portion of the collector layer over which one or more HFETs are fabricated; forming one or more channel regions 20,22 over the buffer region; forming a wide bandgap material emitter/gate layer 26 over the base pedestal and the channel region; forming isolation regions 30,32, whereby there is one or more separate HBTs and one or more separate HFETs over the substrate utilizing an epitaxially grown emitter/gate layer to form both an HBT emitter and an HFET gate. Other devices and methods are also disclosed.

Abstract: Disclosed is a scaled, self aligned, bipolar transistor and a method of fabrication which is compatible with MOSFET device structures. A transistor intrinsic base region is formed in the face of an isolated epitaxial region and polysilicon is deposited, patterned and etched to form emitter regions. An oxide cap and first sidewall oxide spacers are formed on the polysilicon emitters and the single crystal silicon is etched using the oxide covered emitters as a mask to form recessed regions in the epitaxial layer. The extrinsic base region is then formed adjacent at least one side of the base by implanting appropriate dopants into one of the recessed regions. A second sidewall oxide spacer is then formed on the vertical base emitter structure and a heavily doped collector contact region is formed by implanting appropriate dopants into another one of the recessed silicon regions.

Abstract: This is a vertical MOSFET device with low gate to drain overlap capacitance. It can comprise a semiconductor substrate 22 of the first conductivity type, a source region 24,26 of a second conductivity type formed in the upper surface of the substrate 22; a vertical pillar with a channel region 28 of the first conductivity type, a lightly doped drain region 30 of the second conductivity type and a highly doped drain contact region 32 of the second conductivity type; a gate insulator 34, and a gate electrode 36 surrounding the vertical pillar not substantially extending into the highly doped drain contact region 30.

Abstract: The invention is structured to add each output signal of a plurality of signal converters connected in parallel, after a common signal is inputted to and quantized in the above plurality of signal converters, having a noise generators which input noise generated utilizing random variables unrelated to each other to respective quantizers within the above plurality of signal converters, so that quantization noise, Q, or the like can be effectively averaged, and a highly reliable signal conversion device, which can ensure an enough dynamic range across a wide frequency region, can be provided.Also, the invention is structured to add each output signal of a plurality of signal converters connected in parallel, after a common input signal is inputted to and quantized in the above plurality of signal converters, so that a highly reliable signal conversion device similar to the above can be provided.

Abstract: A new class of CMOS integrated circuits, wherein the PMOS and NMOS devices are both configured as vertical transistors. One trench can contain a PMOS device, an NMOS device, and a gate which is coupled to control both the PMOS device and the NMOS device. Latchup problems do not arise, and n+ to p+ spacing rules are not required.

Abstract: This digital-analog conversion system comprises a digital modulator (1) having several quantification levels formed by a second order Delta-Sigma modulator and a digital-analog converter and switched capacitors filter set (3) whose law of progression between the different analog levels is independent of the absolute and relative values of the constituent components of the said assembly.

Abstract: An apparatus for treating an object with a liquid in which the object is immersed into the liquid in a tank which has overflow control members provided above faces of the tank with a predetermined space in an overflow area for said liquid, said space being structured to lead the overflow of said liquid by capillary action.

Abstract: A vertical memory cell EPROM array (FIGS. 1, 1a and 1b) uses a vertical floating gate memory cell structure that can be fabricated with reduced cell area and channel length. The vertical memory cell memory array includes multiple rows of buried layers that are vertically stacked--a drain bitline (34) over a source groundline (32), defining a channel layer (36) in between. In each bitline row, trenches (22) of a selected configuration are formed, extending through the drain bitline and channel layer, and at least partially into the source groundline, thereby defining corresponding source (23), drain (24) and channel regions (25) adjacent each trench. The array can be made contactless (FIG. 1a), half-contact (FIG. 2a) or full contact (FIG. 2b), trading decreased access time for increased cell area.

Abstract: A lead from 10 carries an integrated circuit on a die support pad 14. The lead frame has a dam bar including a transverse portion that extends between adjacent leads (20) for limiting mold flash. The dam bar transverse portion 26 is entirely severed from the adjacent leads for final removal by a metal punch 33 along with the supporting web 16.

Abstract: Integrated circuits and fabrication methods incorporating both NPN (192, 194, 210) and PNP (196, 121, 124) heterojunction bipolar transistors together with N channel (198, 200, 216, 218) and P channel (202, 204, 220, 222) JFETs on a single substrate as illustrated in FIG. 10. MESFETs may also be integrated on the substrate.

Abstract: A delay stage (60) has a delay period of reduced dependence on the level of a first voltage supply (V.sub.dd). First and second inverter stages (78, 90) each have p-channel transistors (68, 86) and n-channel transistors (70, 88). The gates (64, 66) of the first inverter pair are connected to an input node (62). A fixed resistor (72) is inserted between the current path of the p-channel transistor (68) of the first inverter pair and a signal node (76). The current path of the n-channel transistor (66) of the first inverter is operable to connect the signal node (76) to ground. A MOSFET capacitor (80) is coupled to the signal node (76), as are the gates (82, 84) of the second inverter transistor (86, 88). The current path of the p-channel transistor (86) of the second inverter is operable to connect the voltage supply (V.sub.dd) to an output node (92), and the current path of the n-channel transistor (88) of the second inverter (90) is operable to connect the output node (92) to ground.

Abstract: Vertical AlGaAs heterojunction bipolar transistors and GaAs junction field effect transistors are fabricated on a single gallium arsenide (GaAs) substrate to form an integrated circuit structure. The integration of these devices is made possible by a novel method of fabricating heterojunction inverted transistor integrated logic (HI2L) transistors with emitter reigons on the bottom (contacted through the substrate) while simultaneously forming the JFET structure with no additional processing steps. An ion implant technique is employed which uses an acceptor material to create a P type region, boron or protons to create insulating regions, and silicon or selenium to create an N type region. A zinc diffusion is used to form the bipolar P type ohmic contact regions and JFET gate regions in one operation. Bipolar collector and JFET source and drain metallization patterns are formed simultaneously followed by the simultaneous formation of bipolar base and JFET metallization patterns.

Abstract: A programmable device (10) is formed from a silicided MOS transistor. The transistor (10) is formed at a face of a semiconductor layer (12), and includes a diffused drain region (17, 22) and a source region (19, 24) that are spaced apart by a channel region (26). At least the drain region (22) has a surface with a silicided layer (28) formed on a portion thereof. The application of a programming voltage in the range of ten to fifteen volts from the drain region (17, 22) to the source region (19, 24) has been discovered to reliably form a melt filament (40) across the channel region (26). A gate voltage (V.sub.g) may be applied to the insulated gate (14) over the channel region (26) such that a ten-volt programming voltage (V.sub.PROG) will cause melt filaments to form in those transistors to which the gate voltage is applied, but will not cause melt filaments to form in the remaining transistors (10) of an array.

Abstract: Method of encoding speech at medium to high bit rates while maintaining very high speech quality, as specifically directed to the coding of the linear predictive (LPC) residual signal using either its Fourier Transform magnitude or phase. In particular, the LPC residual of the speech signal is coded using minimum phase spectral reconstruction techniques by transforming the LPC residual signal in a manner approximately a minimum phase signal, and then applying spectral reconstruction techniques for representing the LPC residual signal by either its Fourier Transform magnitude or phase. The non-iterative spectral reconstruction technique is based upon cepstral coefficients through which the magnitude and phase of a minimum phase signal are related. The LPC residual as reconstructed and regenerated is used as an excitation signal to a LPC synthesis filter in the generation of analog speech signals via speech synthesis from which audible speech may be produced.

Abstract: A programmable resistor 10 is provided having a resistive element 12. Resistive element 12 includes a substrate 26 formed by a layer of semiconductor of a first conductivity-type. A current path 32 is formed in substrate 26 by a layer of semiconductor of a second conductivity-type. An interface 36 having interfacial traps is formed between current path 32 and substrate 26. A backgate 24 is formed adjacent substrate 26. A first switch 14 selectively couples backgate 24 to a first voltage while a second switch 16 selectively couples backgate 24 to a second voltage.

Abstract: A process is disclosed with integrated steps for fabricating bipolar and CMOS transistors. Mask, patterning and implanting steps are highly integrated to reduce the fabrication complexity. The integrated steps include a split level polysilicon step wherein PMOS and NMOS gate conductors and a bipolar emitter structure is formed. The polysilicon is heavily doped which forms MOS transistor gate electrodes, and another high impurity concentration area which is later diffused into an underlying bipolar base region. Small area, high performance transistors can be fabricated with laterally extending contact strips. Alignment of electrode metallization patterns is thus less critical.

Abstract: An on-chip power supply regulation system for a VLSI circuit such as a dynamic RAM is disclosed. The system includes a high power supply voltage detection circuit and a power supply clamp circuit, where a clamped voltage generated by the clamp circuit biases the functional circuitry when the high power supply voltage detection circuit detects an overvoltage conditions. The bias voltage applied to the functional circuitry in the normal operating condition can be a regulated voltage generated from the power supply voltage. Further included in the disclosed circuit is a burn-in voltage generation circuit and a burn-in voltage detection circuit, which can apply an accelerated voltage which depends upon the applied power supply voltage, when the power supply voltage is higher than during normal operation but lower than in the overvoltage condition enabling the clamp operation.