Abstract: A system and method are provided for generating a reliability assessment of a disk drive. The disk drive includes at least one rotatable disk having a surface, and a slider positioned proximate said surface, the slider having a contour that cooperates with air entrained with the disk surface while the disk is rotating when the disk drive is in an operational condition to provide a lift force to enable the slider to fly over the disk surface, the slider parking on the disk surface while the disk is not rotating when the disk drive is in a shut-down condition, the slider sliding over the disk surface while the disk is in a transitional condition sequencing between the shut-down condition and the operational condition. A predetermined bit pattern is written in the parking region of the disk surface, and a reliability assessment is generated based on the amplitude of a signal generated during reading of the predetermined bit pattern in the parking region while the disk drive is in the transitional condition.

Abstract: An operating system-independent file map generator generates an operating system-independent map of a file stored on a mass storage subsystem, the mass storage subsystem including at least one storage device, the at least one storage device including a series of blocks, and the file being stored on a least device extent comprising at least one block. The generator comprises a file identifier receiver, a query module and a file map entry generator. The file identifier receiver receives a file identifier for the file. The query module queries a volume manager to obtain disk extent information for the file identified by the file identifier, the disk extent information identifying the at least one extent. The file map entry generator generates a file map entry for the file map for the file, the file map entry including the disk extent information obtained by the query module.

Abstract: A new digital data storage system comprises at least one storage device, a memory and a control device. The storage device retrievably stores a series of records. The memory stores at least one descriptor for describing at least one selected format attribute of the records stored by the storage device, the selected format attribute having a plurality of formatting characteristics. The descriptor includes a series of record format flags, each of which is associated one of the series of records in the storage device. Each record format flag has a first condition indicating that the selected format attribute of the associated record has a predetermined format characteristic, and a second condition indicating that the selected format attribute of the associated record has a format characteristic which is identified elsewhere in the descriptor. The control device uses the record format flags of the descriptor in connection with retrievals of ones of the records from the storage device.

Abstract: A system for facilitating determination of accurate timing of execution of a computer program fragment by a digital computer comprises a clock resolution determination subsystem and an iteration number determination subsystem. The clock resolution determination subsystem determines a clock resolution value representing a resolution of a clock provided by the digital computer. The iteration number determination subsystem uses the clock resolution value, and maximum and minimum desired time interval values, to determine an iteration number value, the iteration number representing a number of iterations for execution of the computer program fragment to provide accurate timing of the computer program fragment by the digital computer.

Abstract: A system for generating a "where graph" for a parallel processing system comprising a parallel processing array controlled by a control processor. The processing array comprises a plurality of processing elements each processing a program comprising a main routine and a plurality of subroutines, the main routine calling at least one subroutine and at least some of said subroutines calling others of said subroutines. The control processor determines a consolidated program routine sequence identifying sequences of routines extending from said main routine to a current routine being processed by said at least some of said processing elements and generates and displays, on, for example, a video display, the program routine sequence in graph form. The graph comprises a plurality of graph nodes, each representing a routine, with the graph nodes being interconnected to depict the consolidated program routine sequence.

Abstract: A digital computer includes an efficient mechanism by which an exception handler can traverse the instruction stream in a reverse direction to identify the instruction which gave rise to the exception condition after a discontinuity in an instruction stream. The digital computer is provided with both a program counter and an "old program counter." For points in an instruction sequence at which a discontinuity may occur, the "branch taken" portion of the instruction stream is provided with a predetermined type of instruction to enable the old program counter to be saved in a predetermined location. When the instruction is executed, the old program counter will contain a pointer to the "branch not taken" portion of the instruction sequence.

Abstract: A mass storage subsystem includes one or more data stores for storing information for access by one or more devices such as host computers, and a cache memory, and connects to a slave mass storage subsystem which provides mirrored storage for the information stored in its (that is, the mass storage subsystem's) data stores. When a host computer is to access information, the information is cached in the cache memory by the data stores, and the host computer will retrieve the information from the cache memory. In addition, the host computers can update information through the cache memory. Over a period of time, the mass storage subsystem gathers statistics relating to cache misses for respective chunks, each chunk comprising a relatively large number contiguous storage locations as maintained by the data stores, and will periodically cache information from entire chunks.

Abstract: A link referral system includes a classification arrangement for classifying Web pages that the system retrieves over the World Wide Web. In assigning a link in a Web page to a particular classification, the classification arrangement originally establishes the classification using the name for the particular section of the Web page in which the link is located. Using statistical analysis of the occurrence of related links within sections of a number of diverse Web pages, some of which are named sections, the system creates classifications of links under both named classifications as well as anonymous classifications of links that co-occur with a high degree of probability. To minimize errors in the statistical analysis, the classification arrangement determines whether different World Wide Web addresses (so-called "URL's) which are used to access the Web pages in fact identify the same Web page.

Abstract: A parallel program development and processing system includes a parallel program development section and a parallel program execution section. The parallel program development section allows a program developer to develop programs for execution by a parallel computer system using a predetermined set of components which can be selected by the program developer, using a graphical user interface, and linked in a dataflow graph that represents the order of operations to be performed by the program on the data to be processed. After the program developer has developed the graph, the parallel program development section generates executable program code from the instances of the components and their interconnections, for execution by a parallel computer. In the executable program code, instances of the components selected by the program developer form executable objects which are executed by the parallel computer under control of a run-time system that includes an execution control object.

Abstract: A system comprises a plurality of devices which communicate over a network. At least one of the devices transmits information to at least one other of the devices in information messages over a virtual circuit established therebetween using the network. The other device can transmit information concerning, for example, predetermined conditions in the other device in connection with the virtual circuit using signalling messages, which are transmitted by the other device over the virtual circuit to the one device. The one device includes a plurality of mailboxes associated with the virtual circuit, and the other device, that is, the device that is to transmit signalling messages, includes a transmit signal queue including a plurality of entries each associated with one of the mailboxes.

Abstract: A system receives an information stream comprising the textual information whose semantic content is to be determined, divides the information stream into a series of elements and classifies each element into one of a plurality of predetermined classifications. The system includes a token generator and a token classifier. The token generator receives the textual information stream, parses the stream to identifies the respective elements, identifies for each element one of a plurality of element types, and generates a token identifying the element type for each element. At least some of the tokens also include a pointer pointing to the actual information associated with the element. The token classifier receives the tokens and classifies them in order.

Abstract: An information transfer system includes a transmitter and a receiver for transferring information over a differential communication link. The transmitter circuit includes a plurality of gated driver circuits each associated with one of a plurality separate phases of a clock signal, all of the gated driver circuits having respective outputs connected to a differential driver. Each gated driver circuit receives at a respective input a respective one of a plurality of selected information signals and transmits it over the communication link in response to the associated clock signal phase.

Abstract: A digital data transfer system comprises a source module and a destination module interconnected by an information transfer medium. The source module initiates a transfer operation in which it transfers a data item and an associated address over an information transfer medium. The address having an aperture identification portion that identifies one of a plurality of apertures. The destination module receives the data item and the associated address from the information transfer medium during the transfer operation, the destination module using the one of the plurality of apertures identified by the aperture identification portion to generate an aperture value for association with the data item. The source module can also initiate a retrieval operation, during which it transfers an address over the information transfer medium to retrieve previously transferred information.

Abstract: A network browser system facilitates browsing of resources in a network, each of the resources having a respective network address. The network browser system includes a browsing control list and a browsing computer. The browsing control list includes at least one network specifier entry that identifies at least a portion of the network, the portion having associated therewith a range of network addresses. The browsing computer is responsive to a browsing request from an operator to initiate a browsing operation in connection with the network. During the browsing operation, the browsing computer generates, from the network specifier entry in the browsing control list, a plurality of browsing request messages that are associated with respective ones of the network addresses in the network address range, and transmits the browsing request messages over the network.

Abstract: A configuration parameter value access system used in connection with a computer system performs an access operation in connection with a configuration parameter in response to a configuration parameter access request from an applications program. Each configuration parameter access request includes a parameter class identifier, a filename and a parameter identifier. The configuration parameter value access system includes a plurality of configuration file path class lists, each of which has at least one entry, each entry defining a storage subsystem path in the computer system's storage subsystem. A file identifier generator tests successive entries of the configuration file path class list identified by the parameter class identifier to determine whether the storage subsystem contains a file which has the filename provided in the configuration parameter access request along a path defined by an entry.

Abstract: A digital data processing system comprises a host information generating device, a mass storage subsystem, and a back-up information storage subsystem. The host information generating device generates information and provides it to the mass storage subsystem for storage. The mass storage subsystem receives the generated information from the host information generating device and transfers the generated information to the storage element for storage, and further transfers the generated information to the back-up information storage subsystem. The back-up information storage subsystem receives and stores the generated information from the mass storage subsystem's control element. The back-up information storage subsystem includes a filter/buffer module, a tape log module and a reconstruction module. The filter/buffer module filters and buffers the information received from the mass storage subsystem and provides the buffered information to the tape log module for storage.

Abstract: A digital electronic circuit device comprises a plurality of circuit elements, a scan chain establishment element, and a unitary clock domain establishment element. The plurality of circuit elements define a plurality of clock domains, and circuit elements in each clock domain perform processing operations under control of a respective domain clock signal. The scan chain establishment element interconnects the circuit elements in a scan chain to facilitate loading and/or retrieval of a scan vector into and/or out of the digital circuit device. The unitary clock domain establishment element establishes a unitary clock domain for the circuit element when the scan chain establishment element is interconnecting the circuit elements in a scan chain.

Abstract: A diagnostic subsystem is used in a digital device in a digital computer system includes a diagnostic register, a device output control circuit and a diagnostic register reset circuit. The diagnostic register includes a plurality of stages each of which is associated with one of the types of transfers over the bus. Each stage is selectively conditionable by the digital computer system's processor. The device output control circuit controls transfers by the digital device over the bus. The device output control circuit enables the digital device, when it is to engage in a transfer, to transfer information correctly when the associated stage is set and to transfer information incorrectly when the stage has the set condition. For transfers in which the one device is to transmit information over the bus, the incorrectly transmitted information causes error checking circuitry in other devices in the system to generate error indications, which are provided to the processor.

Abstract: A system for avoiding exceptional conditions during execution of a program comprises an execution environment for executing the program and a fix-up code generation subsystem. The program comprises an instruction stream comprising a series of instructions, and the execution environment includes an exceptional condition detector for detecting at least one predetermined type of exceptional condition in connection with execution of each instruction in the instruction stream. The fix-up code generation subsystem is responsive to detection by the execution environment of an exceptional condition of the predetermined type in connection with execution of an instruction in the instruction stream for generating fix-up code which, when processed, would avoid the exceptional condition of that predetermined type, and substitutes the fix-up code in the instruction stream for the instruction in the instruction stream for which the at least one exceptional condition was detected.

Abstract: A microprocessor in a computer system processes an instruction stream comprising instructions of a plurality of instruction types including an information retrieval instruction type. The microprocessor comprises a register set, a pending fault flag set, a functional unit, an information retrieval subsystem, and a control subsystem. The register set comprises a plurality of registers, each register for storing information. The pending fault flag set comprises a plurality of pending fault flags each associated with one of said registers, each pending fault flag having selected conditions including a pending fault condition and a no pending fault condition. The functional unit performs processing operations in response to information input thereto. The information retrieval subsystem initiates an information retrieval operation to retrieve of information from said information storage subsystem for storage in a register.