Abstract: An integrated process is shown for the fabrication of one or more of the following devices: (n-) and (p-) channel low-voltage field-effect logic transistors (556/403); (n-) and (p-) channel high-voltage insulated-gate field-effect transistors (557, 405) for the gating of an EEPROM memory array or the like; a Fowler-Nordheim tunneling EEPROM cell (558); (n-) and (p-) channel drain-extended insulated-gate field-effect transistors (407, 560); vertical and lateral annular DMOS transistors (409, 561); a Schottky diode (411); and a FAMOS EPROM cell (562). A "non-stack" double-level poly EEPROM cell (676) with enhanced reliability (676) is also disclosed.

Abstract: A method and system form a globally planar material layer (44) on a semiconductor wafer (32). The method and system consist of a chuck (58) and a chiller (56) to cool down semiconductor wafer (32) to a predetermined temperature in order to condense multiple liquid film layers (38, 40, 42) to produce a globally planar material layer (44) from a suitable condensable process vapor. At least one process energy source (72 and 74) reactively solidifies the liquid films on the semiconductor wafer (32) and may include a remote plasma source, a radio-frequency plasma source, or a photon source. The steps and apparatus for condensing and solidifying the material layer form a progressive globally planar layer on the semiconductor wafer surface.

Abstract: A preferred embodiment of the present invention is a method of forming a device on a semiconductor substrate of a first conductivity type, the method comprising: forming a semiconducting layer on the substrate; etching alignment marks in the semiconducting layer (102); forming a first mask on the semiconducting layer to expose portions of the semiconducting layer; introducing dopants of a second conductivity type opposite the first conductivity type into the exposed portions of the semiconducting layer to form high-voltage tanks (104); removing the first mask; annealing the dopants introduced to form high-voltage tanks of a second conductivity type (105); forming a second mask on the semiconducting layer to expose second portions of the semiconducting layer; introducing dopants of a second conductivity type into the exposed second portions of the semiconducting layer to form low-voltage tanks (106); removing the second mask; forming a third mask on the semiconducting layer to expose third portions of the semi

Abstract: A method for manufacturing semiconductor device having metal leads 14 with improved reliability, and device for same, comprising metal leads 14 on a substrate 12, a low-dielectric constant material 18 at least between the metal leads 14, and thermoconductive insulating layer 22 deposited on the metal leads 14 and the low-dielectric constant material 18, and dummy leads 16 proximate metal leads 14. Heat from the metal leads 14 is transferable to the dummy leads 16 and thermoconductive insulating layer 22, which are both capable of dissipating the heat. A thin thermoconductive layer 24 may be deposited over the metal leads 14 prior to depositing at least the low-dielectric constant material 18 and the thermoconductive insulating layer 22. The low-dielectric constant material 18 has a dielectric constant of less than 3.5. An advantage of the invention is to improve reliability of metal leads for circuits using low-dielectric constant materials.

Abstract: A semiconductor device and process for making the same are disclosed which use porous dielectric materials to reduce capacitance between conductors, while allowing conventional photolithography and metal techniques and materials to be used in fabrication. In one structure, patterned conductors 18 are provided on an interlayer dielectric 10, with a substrate encapsulation layer 32 deposited conformally over this structure. A layer of porous dielectric material 22 (e.g. dried SiO.sub.2 gel) is then deposited to substantially fill the gaps between and also cover the conductors. A substantially solid cap layer 24 of a material such as SiO.sub.2 is then deposited, followed by a photolithography step to define via locations. Vias are etched through the cap layer, and then through the porous dielectric.

Abstract: A semiconductor device and process for making the same are disclosed which incorporate a relatively large percentage of holmium dopant (0.5 to 5%) into a BST dielectric film 24 with small grain size (e.g. 10 nm to 50 nm). Dielectric film 24 is preferably disposed between electrodes 18 and 26 (which preferably have a Pt layer contacting the BST) to form a capacitive structure with a relatively high dielectric constant and relatively low leakage current. Apparently, properties of the thin film deposition and small grain size, including temperatures well below bulk BST sintering temperatures, allow the film to support markedly higher defect concentrations without holmium precipitation than are observed for bulk BST. For holmium doping levels generally between 0.5 and 5% (compensated with titanium and/or manganese), better than 50% improvement in dielectric constant and two to six orders of magnitude reduction in leakage current (compared to undoped BST) have been observed for such films.

Abstract: A chuck (82) for lamp-heated thermal and plasma semiconductor wafer (38) processing comprises an absorbing surface (171) for absorbing optical energy from an illuminator module (84) that transforms the electrical energy into radiant optical energy. Chuck (82) includes an absorbing surface (171) that absorbs optical energy and distributes the resultant thermal energy. From the absorbing surface, a contact surface (168) conducts the heat energy to semiconductor wafer (38) and uniformly heats the semiconductor wafer (38) with the distributed thermal energy. Chuck (82) not only provides significantly improved process temperature uniformity, but also allows for the generation of RF plasma for plasma-enhanced fabrication processes as well as for in-situ chamber cleaning and etching. Additionally, chuck (82) provides at least two methods of determining semiconductor wafer temperature; a direct reading thermocouple (112) and association with the pyrometry sensor of illuminator module (84).

Abstract: A via opening (24) is formed within a semiconductor structure (10) in order to allow for the insertion of a contact to establish multi-level interconnects in an integrated circuit. The via opening (24) extends to a conductive layer (16) within the semiconductor structure (10). During the formation of the via opening (24), a residual layer (26) is created within the via opening (24) and on the exposed surface of the conductive layer (16). A dry plasma material is introduced at the semiconductor structure (10) to remove the residual layer (26) from the via opening (24) and the exposed surface of the conductive layer (16). After removal of the residual layer (26), a conductive material for establishing the contact for connection to the conductive layer (16) is inserted within the via opening (24).

Abstract: A high-speed decoder for salvaging defective memory cells which has voltage generators VG0 and VG3 for generating voltages having binary logic levels corresponding to the bit information of each column of the addresses of defective memory cells. Upon input of a memory address signal, the voltage level of the bits of each column of the address signal are checked against the voltage levels corresponding to each column from the voltage generator. When all of the columns agree, an address agreement signal is generated by an address corroboration circuit including exclusive OR gates EX0 to EX3 and a NAND gate 10.

Abstract: Semiconductor circuit provides an EEPROM programming charge pump (18), and includes a leakage current measuring device (12), a plurality of interconnected current mirrors, and a current controlled oscillator (16) for providing programming power to such EEPROM. The leakage current sensor (12) generates current nonlinearly related to device ambient temperature of the semiconductor circuit, the current mirrors combining and scaling the leakage current (14) with a constant current to provide a composite current altering frequency of the oscillator (16).

Abstract: An arithmetic and logic unit implemented in a memory array.

Abstract: A circuit (100) for high-speed virtual-to-physical address translation and cache tag matching comprises a set-associative memory management unit (112) for producing a first predetermined number, N, of candidate physical address signals (132 and 134), and N candidate address hit signals (150 and 152). A set-associative cache (114) produces a second predetermined number M of address tags (168 and 170) and N-by-M array (M00, M01, M10 and M11) of comparison circuits compare the candidate physical addresses (132 and 134) with address tags (168 and 170) gating by the N address hit signals to generate cache hit signals.

Abstract: A method for selectively etching oxides from the face of a semiconductor layer 10 is disclosed herein. The semiconductor layer 10 has at least first and second oxide regions 12 and 14 formed on the surface thereof. The oxides 12 and 14 may be doped oxides such as BPSG or PSG and/or thermally treated oxides such as a thermally grown oxide or a deposited oxide which is subsequently annealed. Native and chemical oxides are also considered. The semiconductor wafer 10 is heated to a temperature greater than room temperature (e.g., about 25.degree. C.) and a vapor phase hydrogen fluoride etch is performed so that one of the oxides 14 etches away at a rate significantly higher than the other oxide region 12. Other systems and methods are also disclosed.

Abstract: A temperature compensation circuit (54 and 56, FIG. 3 ) is disclosed for maintaining the voltage at a first node. The amount of time the voltage at the first node is maintained is dependent upon the temperature of a temperature sensitive element (96). The circuit comprises a bleed-off transistor (86) and at least one temperature sensitive element (97). The first terminal (90) of the bleed-off transistor (86) is coupled to the first node and the second terminal (88) is coupled to a first voltage level. The control electrode (92) of the bleed-off transistor (86) is coupled to the first terminal (94) of the temperature sensitive element (96). The other pole of the element is coupled to a second voltage level. The element is operable to generate a voltage drop across its poles dependent upon its temperature.

Abstract: A method and resulting structure to provide an antifuse wherein the resistance of the programmed fuse and the line resistance and capacitance are materially reduced relative to the prior art and the procedures involved and the resulting structure of the fuse permit the use of materials not available in prior art antifuses. This is accomplished by providing the fuse on vertical sidewalls of the fuse electrode or beneath a sidewall oxide on the fuse electrode. Since the thickness of the electrode can be controlled to an extent not currently achievable by lithographic means, a much smaller area antifuse is provided using sidewall antifuse as opposed to a planar antifuse.

Abstract: An new horizontal reactor hardware contains a reactor tube with an insulation block and a flange with exhaust outlets. The insulation block provides high temperature control which reduces condensation and process by-product buildup within the reactor tube. A cylindrical flange, which is connected to the end of the reactor tube, provides exhaust outlets integral with and extending from the flange. The exhaust outlets isolate metal components from the process environment. The flange is held in place at the end of the reactor tube by a clamp. The clamp presses the flange against the end of the reactor tube to form a seal at the junction between the reactor tube and the flange.

Abstract: Described is a new high performance CCD image sensor technology which can be used to build a versatile image senor family with the sensors that have high resolution and high pixel density. The described sensor architectures are based on a new charge super sweep concept which was developed to overcome such common problems as blooming and the image smear. The charge super sweep takes place in very narrow vertical channels located between the photosites similar to the Interline Transfer CCD devices. The difference here is that the charge is never stored in these regions for any significant length of time and is swept out using a new resistive gate traveling wave sweeping technique. The charge super sweep approach also allows the fast charge transfer of several lines of data from the photosites located anywhere in the array into the buffer storage during a single horizontal blanking interval.

Abstract: A high speed signal driving scheme is disclosed which reduces timing delays associated with a signal line precharged to a selected voltage by limiting the voltage transition on the signal line from its precharged voltage.

Abstract: A variable frequency oscillator (19) and method of producing an oscillating signal are provided in which a current mirror (12) receives a control current and generates a mirrored current. A capacitor (20) is coupled to the current mirror (12) and charges and discharges through the current mirror (12) based on the direction of the mirrored current. A trigger (22) is coupled to the capacitor (20) and outputs a first voltage level when the capacitor (20) charges to a first voltage threshold and outputs a second voltage level when the capacitor (20) discharges to a second voltage threshold. A switch (14) is coupled to the current mirror (12) and the trigger (22) for changing the direction of the mirrored current based on the output voltage of the trigger (22).

Abstract: The edges of a semiconductor die are moved away from the lead frame leads attached to the die by using a pressure differential across the semiconductor die.