Abstract: A manufacturing defect analyzer, for inspecting assembled printed circuit boards, including a light source, an optical receiver, a computer controller, and a memory. A plurality of key-points are specified for each component mounted to a printed circuit board. A data record characterizing each key-point is then stored in memory. Next, the defect analyzer measures the height of selected key-points relative to reference key-points for each component. Finally, the measured heights are compared with limit values, thereby determining whether each component is defectively attached to the printed circuit board. The data records facilitate inspection of printed circuit boards having components that are available in different package types.

Abstract: An electrical connector assembly used with a daughter board and a back plane that protects the daughter board and the electrical connectors from damage during use. The assembly includes mounting hardware that is attached to the daughter board to prevent it from bending when a high insertion force is used to plug the daughter board onto the back plane. The mounting hardware also prevents the electrical connectors from damage by distributing the insertion force evenly across the connectors. The assembly also includes a protective cover that is attached to the electrical connectors. The protective cover encloses the signal contacts of the electrical connectors that are attached to the daughter board, and swings away automatically to expose the signal contacts when the daughter board is plugged onto the back plane.

Abstract: A method is available for inspecting a printed circuit board and solder paste deposited upon the printed circuit board, whereby both systematic defects occurring during a solder paste deposition process and random defects are located. The printed circuit board is continuously scanned by an inspection head immediately following the solder paste deposition process. Images of the printed circuit board are then analyzed for random defects such as missing solder paste, improper solder paste coverage, and solder bridging. Next, heights of solder paste deposits are sampled. A pattern of light is projected upon selected solder paste deposits, and images of the selected solder paste deposits are captured. Light triangulation techniques are then used for determining the height of each selected solder paste deposit. Variations in the height of solder paste are systematic defects occurring in the solder paste deposition process.

Abstract: An apparatus and method for testing a telecommunication system, which runs telephony applications such as voice-mail, telephone banking systems, automated directory assistance, and multi-branched telephone customer service systems. The apparatus includes a test computer for scheduling and controlling the execution of test scripts, which include commands for generating network signaling, voice data, and digital data used to simulate transactions that typically take place on the telecommunication system; a database for storing the test scripts, test script input data, and test results; channels for running multiple test scripts in parallel; and, serial and voice ports for transmitting and receiving voice data and digital data to and from the telecommunication system.

Abstract: A method of operating automatic test equipment for sampling an electronic signal produced by a device under test, whereby an effective sampling frequency, FEFF, is determined such that FEFF=NFREP, where N is a desired number of data samples and FREP is the repetition frequency of the electronic signal. At least one replication of the electronic signal is then sampled at a rate equal to FACT, where FACT is equal to FEFF/K, and K is a positive integer value other than one. The value, K, and the number of data samples, N, have no common multiplicative values. As a result, the set of data samples, obtained after sampling at least one replication of the electronic signal at the rate FACT, contains all of the data samples that would be obtained by sampling one replication of the electronic signal at the rate FEFF. The set of data samples can then be reordered to facilitate subsequent analysis of the data samples by the automatic test equipment.

Abstract: A manufacturing defect analyzer, for inspecting assembled printed circuit boards, including a light source, an optical receiver, a computer controller, and a memory. A plurality of key-points are specified for each component mounted to a printed circuit board. A data record characterizing each key-point is then stored in memory. Next, the defect analyzer measures the height of selected key-points relative to reference key-points for each component. Finally, the measured heights are compared with limit values, thereby determining whether each component is defectively attached to the printed circuit board. The data records facilitate inspection of printed circuit boards having components that are available in different package types.

Abstract: A printed circuit board tester that compensates for the different propagation length of each channel including a single-input delay cell, at least one multiple-input delay cell, and a multiplexor. The delay cells are connected to one another in a chain. Further, the single-input delay cell is the first delay cell in the chain, and each multiple-input delay cell has the ability to select one of its inputs. A timing signal is applied to each delay cell, and to the multiplexor. The inputs of the multiple-input delay cells are connected to the output of the single-input delay cell, and to the outputs of any preceding multiple-input delay cells in the chain. The single-input delay cell delays the timing signal. Each multiple-input delay cell is programmed by the tester to select one of its inputs; it then delays the selected input. Finally, the multiplexor is programmed by the tester to select either the timing signal or one of the outputs of the delay cells.

Abstract: A line test system for diagnosing and segmenting faults in a switched telephone network. The system includes a remote measurement unit installed at a switch and a test system controller. The test system controller stores data about operating parameters of each of the subscriber lines when they are believed to be free of faults. When a fault is reported, the parameters are measured again. By comparison of the measured parameters with the stored parameters, the fault can be segmented between the premise and the network. Segmentation is performed using knowledge based analysis techniques. The actual source of the fault once it is repaired is also stored by the test system controller. This historical information is used to improve the accuracy of the knowledge based analysis techniques used for segmentation.

Abstract: A guide pin that mounts easily to a back plane including a hollow, elongated body molded from plastic, and a rigid, elongated steel rod. The plastic body has an opening located at one end. The rod is first inserted into a hole in the back plane. The rod is then inserted into the body through the opening. The action of inserting the rod into the back plane causes the rod to frictionally engage the hole in the back plane, thereby securing the guide pin to the back plane. The portion of the steel rod located inside the plastic body gives the guide pin sufficient strength and rigidity for most back plane assembly applications.

Abstract: A tester that produces digital timing signals having fast data rates including multiple groups of timing generators, multiple "exclusive-or" gates, and an "or" gate. Each group of timing generators is connected to an exclusive-or gate, and the output of each exclusive-or gate is coupled to the or gate. The digital timing signals are encoded such that the timing generators in each group may assert timing pulses only during specified cycles within a series of clock cycles. Each combination of timing generators within a group either asserting their respective encoded timing signals, or not asserting any timing signals during the series of clock cycles, generates a unique serial data stream. The serial data streams generated by the groups of timing generators are then combined to produce a new digital timing signal having a data rate that is faster than the data rate of the encoded digital timing signals.

Abstract: A method and apparatus is presented for the automatic generation of boundary scan description language files for integrated circuits incorporating boundary scan circuitry of indeterminate configuration. The user enters basic pin information for the integrated circuit under consideration, along with an identification of which pins are the boundary-scan TAP pins and which are the power and ground pins. The user connects the pins of a sample integrated circuit to the test channels of the apparatus of the invention.

Abstract: An electronic circuit tester for performing digital signal processing on signals generated by an electronic circuit including a multi-processor test computer, a plurality of driver/receiver channels, a plurality of capture instruments, and a plurality of high speed data paths. Capture instruments are programmed by the tester to sample a signal generated by an electronic circuit under test, convert the samples to digital form if necessary, and store the data samples in memory. The data samples are then moved from the memory of the capture instruments to the main memory of the multi-processor for analysis using digital signal processing techniques. After the initial group of data samples are moved from the capture instruments to main memory, subsequent programming of capture instruments and sampling of signals are performed concurrently with the movement and analysis of data samples. Multiple processors and multiple high speed data paths are preferably used to optimize test program throughput.

Abstract: Apparatus and method for testing lines. The apparatus is particularly useful for testing lines in a switched network, such as might be used to electronically route telephone and computer data lines to various offices in an office building. The apparatus includes an AC test source and a DC measurement device located at a near end switch. A DC transform circuit is located at a far end switch. According to the test method, an AC test signal is injected onto a line under test at the near end. At the far end, the received signal is converted to DC, which is sent to the near end. Line attenuation, and hence fault conditions, are detected by comparing the DC signal to the transmitted AC signal. Techniques to increase the signal to noise ratio of the DC signal are also disclosed.

Abstract: A method for automatically testing digital electronic circuits and performing time measurements whereby a digital signal having a frequency f1 is sampled at a rate equal to f2. The sampling frequency f2 is either slightly less than or slightly greater than f1. As a result, the digital signal is sampled at either a slightly later position in time or a slightly earlier position in time during each successive period of the digital signal. After the entire interval of interest on the digital signal has been sampled, either the number of logical high data samples or the number of logical low data samples is determined. Finally, the number of data samples is multiplied by the effective time period between data samples. In this way, pulse widths on digital signals can be measured with both high resolution and good linearity. This method of time measurement may also be used to calibrate an electronic circuit tester.