Abstract: A method and apparatus for maintaining a secure run-time environment in which arbitrary relationships between the subjects and objects of differing sensitivity labels are defined so as to provide for discrete access between arbitrary, normally incomparable sensitivity labels.

Abstract: A CAM providing for the identification of a plurality of multiple bit tag values stored in the CAM, having logic circuitry for comparing each bit of an inputted test value to the corresponding bits of all stored tag values. A bit select is employed for generating a plurality of test bits for sequential input into the logic circuitry. The logic circuitry compares the plurality of test bits to the corresponding bit of each stored tag value and generates a “hit” signal if the selected bit is the same as the corresponding bit of the stored tag value. Storage means are employed for recording the results of the compare with the M hit signal.

Abstract: A patch selection tool providing a method and apparatus for identifying software patches for installation on a computer system in which current versions of software applications installed on the computer system are identified as well as currently installed patches, products, and versions. An initial list of recommended patches is generated based on the combination of the installed products and the validated list of datasheet selected products, a final list is created by modifying the initial list to remove bad or outdated patches.

Abstract: The invention provides a method for automated matching of retention times obtained using a known chromatographic method having a defined set of column parameters and operating parameters to the retention times obtained using a new chromatographic method having a new set of column parameters, wherein the retention times of components separated in accordance with the new chromatographic method are matched to the retention times set forth in the known chromatographic methods. A procedure is described to adjust head pressure to compensate for differences in a new versus the original column, carrier gas, and column outlet pressure of the known method.

Abstract: Screening an unknown sample for a plurality of known or "target" analytes may be accomplished by creating and searching a retention time-locked spectral database for the entire chromatographic output of a locked GC system locked to such spectral database. Identification of target analytes having for example, known significant mass spectral ions and mass ion ratios corresponding to known analytes of interest believed to be found within a pre-defined retention time window is improved by direct comparison of significant mass spectral ions and the mass ion ratios within a specified retention time window.

Abstract: The present invention is a secure Web platform (SWP) implementing a mandatory access control policy to enable a plurality of remote users operating Web browsers Internet access to CGI applications in response to HyperText Transfer Protocol (HTTP) requests. The SWP employs a computer having a compartmentalized process and file structure separated in accordance with a mandatory access control policy into an outside compartment comprising a Web server having a root directory chrooted to a directory tree containing only the minimal set of files required to interface the SWP with the Internet, and an inside compartment comprising a plurality of CGI applications having root directories chrooted to a directory separate from the Web server such that the Web server cannot communicate directly with the CGI applications, and a trusted gateway agent for communicating between the Web server and the CGI applications.

Abstract: The present invention provides asymmetric bidentate silane reagents from modifying the surface of liquid chromatography supports, the supports and methods of making and using the same. When bonded to the surface of a support material, the resulting modified support material provides improved properties, such as better separations and more stable support materials, especially when used in liquid chromatography. These bidentate silanes have the general structure: R.sub.1 SiMe(NMe.sub.2)--(CH.sub.2).sub.n --SiMeR.sub.2 (NMe.sub.2). R.sub.1 is an alkyl group having from 1 to 30 carbon atoms, and R.sub.2 is an alkyl group having from 8 to 18 carbon atoms. R.sub.1 is a different alkyl group than R.sub.2. Me is a methyl group, and n has a value 2 or 3. In certain embodiments, R.sub.2 includes at least one functional group. When reacted with a silica surface, the resulting modified surface has a structure: PSiO--?R.sub.1 SiMe--(CH.sub.2).sub.n --SiMeR!--OSiP. PSiO is a surface reacted silica.

Abstract: A simplified method and apparatus for electronic pressure control with compensation for current operating temperature and pressures in which computer memory is employed for storing a plurality of firmware models which characterize the effects of temperature and pressure variations on (1) fluid flow through the flow restrictor, (2) the temperature sensor, and (3) the pressure sensor, so that control signals can be generated which compensate a plurality of thermally coupled sensors for changes in current operating temperatures and pressures.

Abstract: The invention provides a method for developing a retention time database of identified analytes and their respective retention times in a reference Gas Chromatograph (GC) system under locked conditions for identification of unknown analytes of interest eluting from any GC system locked to the retention time database and may also be employed in combination with selective detection and or method translation for enhanced certainty of identification.

Abstract: An integrated circuit having an internal switch including remap-multiplexers that are actuated through either hardware or firmware for remapping external addresses such that the IC switches between a standard and a reverse pin assignment to simplify lead routing between a plurality of integrated circuits mounted on a PC board.

Abstract: A method and apparatus for non-liquid solvent introduction of analyte into an analytical instrument and, more particularly, to a bonded liquid phase analyte trap with integral flow switching that may include a rapid solid-state heating and cooling device. The analyte trap includes a first wafer having a flow channel formed on its bottom side such that a second wafer attached to the bottom side of the first wafer encloses the flow channel and a stationary phase coating is chemically bonded to the walls of the flow channel to provide a mechanism for trapping analytes of interest.

Abstract: A simplified method and apparatus for electronic pressure control with compensation for current operating temperature and pressures in which computer memory is employed for storing a plurality of firmware models which characterize the effects of temperature and pressure variations on (1) fluid flow through the flow restrictor, (2) the temperature sensor, and (3) the pressure sensor, so that control signals can be generated which compensate a plurality of thermally coupled sensors for changes in current operating temperatures and pressures.

Abstract: The invention is a method and apparatus for transmitting frames from a plurality of node ports (N.sub.-- ports) to their associated fabric ports (F.sub.-- ports) for forwarding to other interconnected F.sub.-- ports on a Fibre Channel switch in which the transmitted frames are stored in a plurality of receive buffers at the associated F.sub.-- port prior to forwarding to an interconnected F.sub.-- port, and a receive credit counter, a smart credit counter and a transmit credit counter are employed for tracking the availability of the receive buffers.

Abstract: A channel module has an interchangeable port intelligence system at a front end which is connected to a memory interface system at a back end. Each port intelligence system provides one or more ports for connection to fiber optic channels and, the various port intelligence systems are distinguishable by a particular bit rate in which each supports. Data from the port intelligence system is bit sliced and forwarded to the memory interface system. In the system, the data is stored in receive memory in a distributed manner over a plurality of receive memory components. The bit slicing simplifies the input/output interface to the receive memory and enables storage of data with a common format, regardless of the rate at which the data was received from the channel. When data is read from the receive memory, each of the receive memory components contributes bits in order to reconstruct the data.

Abstract: A diagnostics tool having a graphical user interface coupled to an instrument from a remote location for inspecting instrument variables, parameters and set-points, performance testing, as well as, managing information resources necessary to repair the instrument to provide fast and accurate diagnosis of problems and faults within the instrument.

Abstract: A method and apparatus for high speed decoding of a 20 bit wide data into 16-bit wide data in which the first ten bits and the lower ten bits are decoded simultaneously to ensure complete decoding and where the decoding of the second ten bits is dependent upon the running disparity of the first ten bits, the second ten bits are decoded twice, one assuming the decoded first ten bits will have a positive running disparity, and a second time assuming that the decoded first ten bits will have a negative running disparity.

Abstract: A fiber optic switch interconnects fiber optic channels so that a fiber optic network can be implemented. Channel modules provide ports (p1-pi) for connection of the fiber optic channels. Each channel module has a receive memory for temporarily storing incoming data frames from the fiber optic channels associated therewith. A switch module having a data distribution network interconnects each of the channel modules and permits ultimate connection of a source channel to a destination channel. A path allocation system, which controls the switch module, allocates the data paths between the channels. The path allocation system has a scheduler which maintains a destination queue (Q.sub.p1 -Q.sub.pi) for each of the channels, a sentry which determines when a new data frame is ready to be routed, and an arbitrator which arbitrates port availability and which grants transfer requests proposed by the scheduler.

Abstract: The invention is a diagnostic tool for providing remote diagnosis of instrument operation by graphically depicting an instrument, instrument variables and their corresponding values on a plurality of interrelated windows displayed on a computer screen. The computer communicates with the instrument to obtain signals for continuously updating the information displayed on the windows.

Abstract: A simplified method for solid phase extraction of components of interest from a sample employing a syringe in which the inner surface of the cannula or needle is at least partially coated with a stationary phase such that aspirating the sample into the needle results in adsorption of the components of interest into the stationary phase. Aspiration of a solvent may be employed for removing the components of interest from the stationary phase for direct injection into a chromatographic instrument, or the components of interest may be removed by thermal desorption, wherein the needle is placed in the injection port of the chromatographic instrument and heated.

Abstract: A frame time monitoring system tracks the time in which data frames reside within a fiber optic switch for a fiber optic network. The network switch transfers data frames from source ports to destination ports. The frame time monitoring system comprises a digital signal processor (DSP), which is configured by a software program to implement a plurality of timers relative to frames to be routed through the switch from a source port to a destination port. The processor operates as an incrementer and is configured to output a series of sequential timer states corresponding to each particular frame. The timer states are generally indicative of the amount of time in which the frame has resided in the switch. A logic network of logic gates is connected to the processor to receive and interpret the timer states. The logic network has frame busy (FBSY) and delete mechanisms for determining elapse of respective FBSY and delete time periods based upon the timer states.