Patents Represented by Attorney, Agent or Law Firm Richard L. Hughes
  • Patent number: 6631382
    Abstract: Generation of output or reports on information contained in a data source which may be any of two or more types of source data, in a standardized or uniform manner is provided. A plurality of drivers are provided specific to different types of source data which include programming for identifying structural or other characteristics of the various data sources, e.g. for use in defining a new database. Preferably the new database is configured to permit highly flexible and/or rapid output or reporting or is otherwise optimized for reporting purposes. In one embodiment, the present invention includes conversion of one or more data sources into one or more uniform databases, preferably generating one or more key categories for organizing the data, optionally generating category groupings or rollups and additional data or optional references.
    Type: Grant
    Filed: July 31, 2000
    Date of Patent: October 7, 2003
    Assignee: Timeline, Inc.
    Inventors: David B. Kouchi, David Yarnall, Donald K. Babcock
  • Patent number: 6205837
    Abstract: A support device or post for fitting into an implant implanted into a patient which is configured to support a dental prosthesis is provided. An upper portion of the post, in one embodiment, has external screw threads for coupling a healing cap. The upper portion of the post may be removed or broken away at a weakened portion or constriction. The support device has a collar which can define various heights or diameters. The support device can be positioned in the implant by mating screw threads with the support device being torqued to a predetermined torque, preferably using a torque wrench which can be set using a non-variable, preferably gravity-based, standard.
    Type: Grant
    Filed: May 27, 1999
    Date of Patent: March 27, 2001
    Inventor: Stanley W. Sapkos
  • Patent number: 5466960
    Abstract: A well tap for a field effect device formed using a single polysilicon process and a silicide layer is provided. The polysilicon layer which makes contact to the well is doped the same way as the well but is doped opposite of the source or drain. The silicide layer is formed on the upper and sidewall surfaces of the source or drain, well tap, and gate contacts for a field effect device. The silicide layer extends from the sidewall silicide across the upper surface of the transistors and up to the sidewall oxide of the transistor gates. The structure makes it possible to eliminate laterally-spaced separate well taps used in previous devices. Elimination of the laterally-spaced well taps permits higher packing density, and lowers buried layer-to-substrate capacitance.
    Type: Grant
    Filed: August 20, 1991
    Date of Patent: November 14, 1995
    Assignee: National Semiconductor Corporation
    Inventors: Vida Ilderem, Steven M. Leibiger
  • Patent number: 5208838
    Abstract: A clock multiplier is selectable to provide either an unmultiplied input clock to the internal clock line or a multiplied clock signal, depending upon the state of a test mode input signal. By providing the circuitry on a integrated circuit chip, the chip can be driven at its normal operating frequency using lower-frequency test equipment. One multiplier device includes a plurality of series-connected one-shots.
    Type: Grant
    Filed: March 30, 1990
    Date of Patent: May 4, 1993
    Assignee: National Semiconductor Corporation
    Inventors: Dennis L. Wendell, Charles Hochstedler, Dan Lunecki, Terry L. Lyon
  • Patent number: 5160859
    Abstract: A clock signal for use in a BiCMOS device is driven over a high capacitance wire at ECL levels. Local CMOS circuits are activated using local ECL-to-CMOS translators. This configuration reduces clock signal delay and skew and provides for greater temperature independence.
    Type: Grant
    Filed: October 22, 1990
    Date of Patent: November 3, 1992
    Assignee: National Semiconductor Corporation
    Inventor: Dennis L. Wendell
  • Patent number: 5155391
    Abstract: A clock signal for use in a BiCMOS device is driven over a high capacitance wire at ECL levels. Local CMOS circuits are activated using local ECL-to-CMOS translators. This configuration reduces clock signal delay and skew and provides for greater temperature independence.
    Type: Grant
    Filed: January 16, 1991
    Date of Patent: October 13, 1992
    Assignee: National Semiconductor Corporation
    Inventor: Dennis L. Wendell
  • Patent number: 5153882
    Abstract: A scan diagnostics apparatus and method is useful in connection with the memory integrated circuit. A shift register is provided which can receive data in parallel from the input register and output the data serially. The shift register can receive serial data and output in parallel either to the input buffer or the output buffer. Preferably the shift register can receive in parallel, data from the output buffer and output the data serially.
    Type: Grant
    Filed: March 29, 1990
    Date of Patent: October 6, 1992
    Assignees: National Semiconductor Corporation, Control Data Corporation
    Inventors: Terry L. Lyon, Jeff Chritz
  • Patent number: 5144171
    Abstract: A high-speed differential-feedback cascode sense amplifier includes an output stage and a voltage clamp. The voltage clamp is coupled to a pair of bit-sense lines of a memory system or other sense line source. The output stage is coupled to the output of the voltage clamp for generating an output signal having a logic state determined according to the current difference across the bit-sense lines. The voltage clamp includes a pair of transistors (e.g., cascode transistors) in cascode to a differential-feedback gain stage. Bit-sense lines are coupled to the cascode transistors and the differential-feedback gain stage. The gain stage amplifies the current difference across the bit-sense lines to define feedback voltage signals input to the cascode transistors. The parasitic voltage difference across the bit-sense lines resulting from driving the cascode transistors is small, approximately 3-7 mV for an ECL sense amplifier.
    Type: Grant
    Filed: November 15, 1990
    Date of Patent: September 1, 1992
    Assignee: National Semiconductor Corporation
    Inventor: Jeffrey M. Huard
  • Patent number: 5139966
    Abstract: Low resistance contacts for establishing an electrical pathway to an integrated surface substrate are provided. The pathway is formed by the connection of a p+ doped channel stop region with a p+ doped extrinsic layer. P+ doped polysilicon contacts are positioned on the substrate surface. In one embodiment, a metal silicide layer connects the polysilicon contacts and overlies the p+ doped extrinsic layer.
    Type: Grant
    Filed: April 2, 1990
    Date of Patent: August 18, 1992
    Assignee: National Semiconductor Corporation
    Inventors: Rick C. Jerome, Frank Marazita
  • Patent number: 5109256
    Abstract: A Schottky diode is formed with a layer of intrinsic polysilicon separating a metal silicide layer from an n conductivity type active region. This structure avoids the necessity for a process step which opens a window in the intrinsic polysilicon layer and reduces the portion of surface area needed for formation of a Schottky diode, compared to previous devices. The Schottky diode can be formed as part of an overall process for forming an integrated circuit and can be positioned in parallel across the collector/base junction of a bipolar transistor to form a Schottky barrier diode-clamped transistor.
    Type: Grant
    Filed: August 17, 1990
    Date of Patent: April 28, 1992
    Assignee: National Semiconductor Corporation
    Inventor: Bancherd De Long
  • Patent number: 5079182
    Abstract: A well tap for a field effect device formed using a single polysilicon process and a silicide layer is provided. The polysilicon layer which makes contact to the well is doped the same way as the well but is doped opposite of the source or drain. The silicide layer is formed on the upper and sidewall surfaces of the source or drain, well tap, and gate contacts for a field effect device. The silicide layer extends from the sidewall silicide across the upper surface of the transistors and up to the sidewall oxide of the transistor gates. The structure makes it possible to eliminate laterally-spaced separate well taps used in previous devices. Elimination of the laterally-spaced well taps permits hgher packing density, and lowers buried layer-to-substrate capacitance.
    Type: Grant
    Filed: April 2, 1990
    Date of Patent: January 7, 1992
    Assignee: National Semiconductor Corporation
    Inventors: Vida Ilderem, Steven M. Leibiger