Abstract: An opening (24) is formed in a substrate (20). A first layer (30) is formed over the substrate (20) and the feature opening (24). A second layer (40) is formed over the first layer (30) and then the second layer is removed until exposing portions (50) of the first layer (30). The exposed portions (50) of the first layer (30) are then optionally removed using remaining portions (52) of the second layer (40) as a patterning mask to form a cavity (60) in the first layer (30). The remaining portions of the second layer (52) are then removed and the first layer (30) is polished to form a semiconductor device structure (80). In one embodiment, the first layer is dielectric layer, and in an alternative embodiment, the first layer is a conductive layer.

Abstract: A dielectric film (110) is formed overlying a semiconductor device substrate (10). A dielectric post (204) having an outer peripheral boundary having sidewalls is formed over the dielectric film (110). A first conductive film (402) is deposited at least along the sidewalls of the dielectric post (204) to form a lower electrode. A capacitor dielectric film (1801) is deposited on the first conductive film, and a upper electrode (1802) is formed on the capacitor dielectric film (1801).

Abstract: An electrically erasable programmable read only memory (EEPROM) array (30) that includes rows and columns of memory cells. Word lines (WL0 and WL1) are substantially parallel to each other and extend in a first direction. Drain bit lines (BL0-B13) and source lines (SL0 and SL1) are substantially parallel to each other and extend in a second direction that is perpendicular to the first direction. The source line (SL0) and source regions of at least two memory cells (31 and 36) within the EEPROM array are electrically connected by a first source local interconnect (LI1). The first source local interconnect (LI1) has a length that extends substantially in the first direction and electrically connects some, but not all, of the memory cells lying within the EEPROM array (30).

Abstract: Metal semiconductor nitride gate electrodes (40, 70) are formed for use in a semiconductor device (60). The gate electrodes (40, 70) may be formed by sputter deposition, low pressure chemical vapor deposition (LPCVD), or plasma enhanced chemical vapor deposition (PECVD). The materials are expected to etch similar to silicon-containing compounds and may be etched in traditional halide-based etching chemistries. The metal semiconductor nitride gate electrodes (40, 70) are relatively stable, can be formed relatively thinner than traditional gate electrodes (40, 70) and work functions near the middle of the band gap for the material of the substrate (12).

Abstract: A process for fabrication of a multilevel interconnect structure includes the formation of an inlaid interconnect (42) overlying an aluminum layer (34). The inlaid interconnect (42) is formed within an interlevel dielectric layer that is processed to contain an interconnect channel (24) and a via opening (14) residing at the bottom of the interconnect channel (24). The aluminum layer (34) is selectively deposited to fill the via opening (14) at the bottom of an interconnect channel (24). Selective deposition is enhanced by the use of a nucleation layer (20) which is formed on the bottom of the via opening, without being formed on the sidewalls, by use of directional deposition technique such as inductively coupled plasma (ICP) deposition. Nucleation layer (20) eases requirements of a cleaning operation prior to selective deposition and provides a surface from which void-free selective growth can occur.

Abstract: Deuterated compounds are used to form passivation (20) and other insulating layers to reduce the hydrogen content within those films. Semiconductor source gases, nitride source gases, and dopant gases can be obtained in deuterated form. Process steps for forming and etching are substantially the same as those used to form and etch conventional insulating layer. A sintering step can be performed using deuterated gas or omitted altogether.

Abstract: A method of forming a semiconductor device includes providing a substrate (10) and depositing a gate dielectric (12) overlying the substrate (10). A gate is formed overlying the gate dielectric (12). The gate has a first sidewall and comprises a metal-containing layer (14) overlying the gate dielectric (12). A first spacer layer (20) is deposited over the gate and the substrate (10). A portion of the first spacer layer along the first sidewall forms a first spacer (22). A liner layer (30) is deposited over the gate and the substrate (10), and a second spacer layer (32) is deposited over the liner layer (30). The second spacer layer (32) is etched to leave a portion of the second spacer layer (32) along the first sidewall to form a second spacer (34). Also disclosed is a metal gate structure of a semiconductor device.

Abstract: Alignment of a blade (60) to an electrostatic chuck (53) is accomplished using an alignment tool (30) and an alignment pin (40) to align a port (534) in the electrostatic chuck (53) directly to a hole (602) in the blade (60). Placement of a substrate (70) in a processing chamber (50) is accomplished using a substrate handler configured with the blade (60) to place the substrate (70) accurately on the electrostatic chuck (53). The substrate (70) is then processed in the processing chamber (50) using the electrostatic chuck (53).

Abstract: In one embodiment of the invention, conductive support structures (112) are formed within an interlevel dielectric layer. The conductive support structures (112) lie within the bond pad region (111) of the integrated circuit and provide support to portions of the interlevel dielectric layer that have a low Young's modulus. The conductive support structures (112) are formed using the same processes that are used to form metal interconnects in the device region (109) of the integrated circuit, but they are not electrically coupled to semiconductor devices that lie within the device region (109). Conductive support structures (114) are also formed within the scribe line region (104) to provide support to the interlevel dielectric layer in this region of the integrated circuit.

Abstract: Beveled clamp fingers (48) are used in an etching system. The beveled top surfaces (40) of the clamp fingers allow etching species to attack more readily the layer being etched at locations near the beveled clamp fingers (48), thereby reducing the size of halo regions (622). In other embodiments, triangular clamp fingers (78) or clamp fingers (88) with rounded top surfaces can be used.

Abstract: The present invention is a process for forming a lower capacitor electrode. Specifically, an oxygen tolerant bottom electrode layer (312) is formed over a conductive plug (216). A dielectric layer (420) is deposited and partially removed in order to form an inlaid bottom electrode structure. A capacitor dielectric (810) such as BST is formed over the lower electrode (310). The upper electrode (812) is formed over the capacitor dielectric (810) and the resulting stack is patterned in order to form a final capacitive device (916). In another embodiment of the present invention, a hardmask is formed over the bottom electrode (310) and removed prior to the capacitor dielectric (810) being formed.

Abstract: A method of bumping a semiconductor device, including the steps of providing a semiconductor device (100) having a plurality of bumping sites (104), providing a plurality of solder spheres (210), providing a stencil (200) having a plurality of stencil sites (202), each stencil site (202) having a depression and a through hole (204) extending through the stencil(200), placing the plurality of solder spheres (210) on the stencil such that each stencil site of the plurality of stencil sites (202) holds a single solder sphere of the plurality of solder spheres (210), applying a vacuum to the plurality of solder spheres (210), through the vacuum through holes (204), aligning the plurality of solder spheres (210) with the plurality of bumping sites (104) of the semiconductor device (100), releasing the vacuum to release the plurality of solder spheres (210) from the stencil (200) such that the plurality of solder spheres (210) is placed on the plurality of bumping sites (104), and reflowing the plurality of solder