Abstract: A graphics subsystem using a smart DMA controller to perform DMA data loading with some modified addressing. The DMA controller can operate in an incremental mode, in a hold mode (where each chunk of data is written into the same address), or in an indexed mode. The buffer registers are assigned to groups, and, in the indexed mode, a header in the DMA buffer precedes any data for a group. The header identifies the recipient group and each register (in the group) to be updated has its corresponding bit set. Thus a high-efficiency DMA operation is obtained even in cases when increment mode cannot be used directly, e.g. when not all registers in a group need to be written, and/or the registers which need to be written are not contiguous.

Abstract: A computer system having a pixel processing unit with multiple subprocessors receives positional data defining graphical objects from the CPU and writes pixel data into the image memory, and a display driver produces an image which partially includes the rendered pixels. The pixel processor is used to access patches of multiple contiguous pixels at a time, and process them in parallel. The patches used are defined, within the overall geometry of the image, to have aligned corners. The unit is also connected to receive synchronization signals from the display driver, conditioned on whether the current line being accessed by the driver is within a specified range of lines in the image space.

Abstract: A process for making a package for discrete semiconductor devices, wherein the insulating characteristics of the package are increased by introducing cuts, grooves and positioning holes in the metal plate and shaping in the retractable positioning pins of the metal plate in the molding die.

Abstract: A power converter which transfers energy from an output circuit coupled to a secondary winding of a power transformer to an input circuit coupled to a primary winding of the power transformer in order to reduce the power loss and electromagnetic interference (EMI) originating from a primary switch. The reciprocating action of the converter is accomplished by placing the series switched path of a secondary switch in parallel with a diode in the output circuit. A control circuit is coupled to the primary switch and the secondary switch which allows the inherent capacitance of each switch to discharge before turning on the respective switch, thereby reducing the EMI and power losses occurring at these switches. The control circuit includes feedback and feedforward voltage control of the switching duty cycle. The control circuit varies the energy transferred from the output circuit to the input circuit according to changes in the accumulated charge on the primary switch.

Abstract: A rendering system with multi-pixel span processing capability. When 3D graphics processes are not required, 2D data is processed in multi-pixel span fragments. Span fragments permit parallel processing of multiple pixels in a serial architecture, and permit VRAM block fills for accelerated processing under optimal conditions.

Abstract: A process for making an electronic device structure which comprises a metal plate, a semiconductor material chip attached to the plate, terminal leads, interconnection wires between the leads and metallized regions of the chip, and a plastic body which encapsulates the whole with the exception of a surface of the plate and part of the leads. This structure has means of electrical connection between at least one metallized region and the metal plate which comprise at least one metal beam resting onto the plate and being attached thereto by studs integral with the plate, and at least one wire welded between a metallized region of the chip and the metal beam between the studs. At least a portion of the beam and its connection wire are encapsulated within the plastics body.

Abstract: A reading circuit for a multibit register has a differential stage that is configured as an output latch by one of two control phases required by the circuit after the discrimination phase of a reading cycle a single NOR gate, the output of which is provided with anti-overshoot means, enables the performance of a reading cycle. An input of the differential stage, is connectable to a common sensing line to which all the cells of the register are coupled in an OR configuration, while the other input is connectable to a reference current generator.

Abstract: A 3D graphics system in which a pre-rendering stage is combined with a rendering stage. Any GUI window which is not completely displayed on-screen (because it extends past screen boundaries or is overlapped by other windows, etc.), is divided into at least two portions, e.g. rectangles, for scissoring operations. If a primitive appears at least partially in some rectangle, rendering setup data is calculated, then applied against each rectangle in which it appears for a scissoring operation, and the portion of the primitive in that rectangle which survives the scissor is then rendered. The rendering data is stored between each scissoring function, and is not recalculated. Any portion of the primitive which does not appear in a rectangle is not rendered, thereby eliminating any rendering overhead for any primitive which would be completely hidden anyway.

Abstract: A variable-input-voltage variable-switching-frequency power converter with a minimum frequency limit. The switching frequency never goes below a certain minimum while the converter is on. Thus switching frequency is dependent on input voltage, for input voltages in one range, and is NOT dependent on input voltage, for input voltages in another range.

Abstract: A portable computer system including sealed acoustic suspension speaker enclosures which are each molded of a high density-low-density polymer combination, so that the low-density polymer can provide good sealing to adjacent surfaces. Preferably, neither speaker enclosure is sealed as a free standing unit, but the acoustic seal is completed only when the speaker enclosure is in place inside the portable computer.

Abstract: The present invention relates to a memory device and specifically the multilevel type with error check and correction function and having a data input (DI), a data output (DO) and an address input (A1) and being of the type comprising first memory, circuit (DM) designed to be accessed by means of address for containing user data, second memory circuit (EM) for containing error data concerning said user data, a control logic (CL) designed to receive in the writing phase from said address input (A1) and the data input (DI) a writing address and user data respectively and to generate error data and to write, the data in the first circuit (DM) and second circuit (EM) respectively and designed to receive in the reading phase from said address input (AI) a reading address and extract corresponding user data and error data and combine them to correct any errors and supply them to the data output (DO) and characterized in that the second, circuit (EM) is the type designed to be accessed by means of content and, the c

Abstract: Integrated circuits can have both a microprocessor and an internal read-only memory of programs on one and the same chip. To facilitate the perfecting and finalizing of the programs of the read-only memory without undertaking the manufacture, for the perfecting and finalizing operation, of a special version of the circuit that is far too different from the definitive version, an external memory is used for the perfecting and finalizing operation. A contact pad of the chip is used for the transmission, in series mode, of a program coming from an external memory. A mode selection pad makes it possible to define whether the microprocessor must work in internal ROM mode (the normal mode) or in external ROM mode (the mode for the perfecting and finalizing operation).

Abstract: A digital/analog quadratic converter (DACQ) composed by a pair of linear converters connected in cascade has a direct coupling of the output node of the first converter (DAC1) with a node of a R-2R type resistive network of the second converter (DAC2) corresponding to the LSB stage of the R-2R type resistive network. High impedance nodes, notably the input node of the second linear converter, are advantageously eliminated from the "current path" thus markedly reducing the problems of relatively long settling times of high impedance nodes (having intrinsically large parasitic capacitances associated therewith). The peculiar architecture of the quadratic converter provides also for a remarkable simplification of the circuit.

Abstract: Systems, methods, and probe devices for electronic monitoring and characterization using single-ended coupling of a load-pulled oscillator to a system under test.

Abstract: A switched capacitance circuit, using a switched operational amplifier structure as an input switch of the switched capacitance, is provided with a new biasing circuit. An additional switched capacitor, switched alternately to power supply and to ground, is connected to the output side of the primary switched capacitor. Precision is retained while ensuring a rail-to-rail dynamic range, without requiring boosted control phases. Special arrangements may be implemented for controlling the amplitude of switching spikes when so required. A fully differential embodiment is also feasible with additional advantages.

Abstract: In a method for the decoding of the addresses of a memory, a pulse is generated at output of a filtering circuit at each change of address detected at the address bus to inhibit the address decoder during a determined duration. The filtering signal is applied more particularly to the row decoder which selects a row corresponding to an address applied to the input of the decoder and applies a control voltage to this row. This method is particularly advantageous in low-voltage memories.

Abstract: A graphics subsystem which permits single buffered windows to exist in a double buffered system. Thus ALL the pixels on the screen are ultimately double buffered, but the single buffered should not appear to be double buffered. To support the single buffered windows, certain write operations are modified to write the same half-word of data into both the front and back half-words of an addressed location. This permits non-double buffered windows to remain correct when the RAMDAC.TM. is manipulated to swap buffers.

Abstract: An electronic computation circuit comprises a multiplication operator with a serial input, a parallel input and a serial output, a first register connected by its output to the parallel input of the operator, a second register connected by its output to the serial input of the operator, a third register and a multiplexing circuit to selectively connect at least one data input terminal and the output of the operator to the inputs of the first, second and third registers, and to produce the output of the electronic multiplication circuit. Application to the operations of multiplication, squaring, exponentiation and modular inversion on a finite field denoted GF(2.sup.n).

Abstract: In order to make it possible to ascertain that the programming cycles in an EEPROM type memory have been carried out efficiently, supplementary test cells are provided. A data writing operation is carried out in three successive cycles that consist in the programming of a test cell with a first logic value, a second cycle for the programming of the data elements and a third cycle for the programming of the test cell with a logic value that is complementary to the first one. The state of the test cell enables the detection of power interruptions during programming.

Abstract: A parking citation issuing and enforcement system including an electronic citation writing device and an electronic parking meter. The system includes means whereby data, such as the status of the meter, may be transmitted between the electronic citation writing device and the electronic parking meter. The system also includes the ability to download the data from the electronic citation writing device to a computer for reporting of the citation data as well as the data retrieved from the electronic parking meter. This data cannot be manipulated while in the meter, during transmission to the electronic citation writing device, or during and after uploading to computer. Therefore, the report generated can be used in court to help resolve parking violation disputes.