Patents Represented by Attorney Robert J. Feltovic
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Patent number: 5596278Abstract: A condition indicator assembly (tester) for determining the condition of a main cell, e.g. a battery, is disclosed. The condition indicator assembly may comprise an electrochemical indicator cell connected in series to a auxiliary cell. The indicator cell and auxiliary cell each have an anode, cathode and electromotive force (e.m.f.) of its own. The condition indicator assembly may be permanently connected in parallel to the terminals of a main cell being tested. The condition indicator assembly is thin enough that it may be interated into a label for the main cell. As the main cell discharges, the indicator cell anode clears proportionally to the discharge of one of the electrodes of the main cell to provide a continuous visually discernible indication of the state of charge of the main cell.Type: GrantFiled: September 8, 1995Date of Patent: January 21, 1997Assignee: Duracell Inc.Inventor: Lifun Lin
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Patent number: 5595047Abstract: A package for a battery or other article, comprising a sheet of material bent or folded along a plurality of substantially parallel fold lines 21, 22, 25, 26 to define an upwardly extending substantially flat panel region 15, an upper end locating region 11 extending forwardly from the lower extremity of the said panel region, a first limb 3 extending obliquely downwardly and rearwardly from the forward extremity of the end locating region, a second limb 5 extending obliquely forwardly and downwardly and defining with the first limb a V-section channel region, a lower end locating region 13 extending rearwardly from the lower limb, and a rear panel region 17 extending upwardly from the rear extremity of the lower end locating region and secured to the first mentioned panel region 15.Type: GrantFiled: April 17, 1995Date of Patent: January 21, 1997Assignee: Duracell Inc.Inventors: Jacky M. G. N. Paumen, Rowland Hemming, Kai Hartmann, Marc Beckers
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Patent number: 5593794Abstract: A light transparent moisture barrier useful for preventing moisture from destroying the effectiveness of a moisture sensitive cell condition tester on an electrochemical cell, comprises a plurality of very thin layers of amorphous silicon nitride and a hydrophobic fluorocarbon polymer on a flexible, polymeric substrate. The layers are formed on the substrate by a deposition process such as sputtering. The thickness of any individual layer is less than one micron.Type: GrantFiled: January 23, 1995Date of Patent: January 14, 1997Assignee: Duracell Inc.Inventors: Guang Wei, Bryan C. Lagos, Jack Treger
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Patent number: 5589293Abstract: A sealing and insulating member for a cylindrical galvanic cell wherein said member comprises a plurality of vent membranes of non-circular configuration. The seal can readily be made from mineral filled polyolefin material by injection molding.Type: GrantFiled: December 14, 1990Date of Patent: December 31, 1996Assignee: Duracell Inc.Inventors: Peter J. Pope, Richard B. Willis-Owen
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Patent number: 5578390Abstract: A label for an electrochemical cell with a condition tester for the cell integrated with the label to form a label/tester composite is disclosed. The label/tester composite comprises a thermochromic coating in thermal contact with an electrically conductive coating. The label/tester composite is preferably constructed by applying an adhesive to the inside surface of a heat shrinkable base film forming part of the label. A substructure containing a cured conductive coating and preferably also a thermochromic coating is formed on a releasable web. The substructure is transferred from the releasable web to the inside surface of the heat shrinkable base film and in contact with a portion of the adhesive on the base film. A patterned partition insulating coating is then applied over the transferred conductive coating. The label/tester composite is applied to the cell housing. The integrated tester may be manually activated by depressing one or two regions on the surface of the composite.Type: GrantFiled: September 29, 1994Date of Patent: November 26, 1996Assignee: Duracell Inc.Inventor: John F. Hughen
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Patent number: 5557208Abstract: A thermochromic apparatus for testing dc voltage sources, particularly small, low voltage disposable batteries, employs a very thin resistive heater layer deposited onto a flexible dielectric substrate. A series of thermochromic elements are "stacked" (mounted on top of one another) at a single thermochromic site proximate the resistive heater. During testing current from the battery flows through the resistive layer heats the substrate, causing a series of thermochromic elements mounted on the substrate to undergo visual "temperature events" (such as color changes) at progressively higher temperatures. The thermochromics may be stacked in a series of discrete films, each film containing a dye for one temperature event. Alternatively, the thermochromics may be contained in microcapsules in a common film.Type: GrantFiled: June 7, 1995Date of Patent: September 17, 1996Assignee: Duracell Inc.Inventor: Robert Parker
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Patent number: 5544755Abstract: A package for a battery or other article, comprising a sheet of material bent or folded along a plurality of substantially parallel fold lines (21, 22, 25, 26) to define an upwardly extending substantially flat panel region (15), an upper end locating region (11) extending forwardly from the lower extremity of the said panel region, a first limb (3) extending obliquely downwardly and rearwardly from the forward extremity of the end locating region, a second limb (5) extending obliquely forwardly and downwardly and defining with the first limb a V-section channel region, a lower end locating region (13) extending rearwardly from the lower limb, and a rear panel region (17) extending upwardly from the rear extremity of the lower end locating region and secured to the first mentioned panel region (15).Type: GrantFiled: January 17, 1995Date of Patent: August 13, 1996Assignee: Duracell Inc.Inventors: Jacky M. G. N. Paumen, Rowland Hemming, Kai Hartmann, Marc Beckers
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Patent number: 5532084Abstract: The invention relates to the manufacture of manganese dioxide by a chemical process. The resulting product takes the form of gamma manganese dioxide particles characterized by filament-like protrusions of ramsdellite manganese dioxide jutting out from the surface of the particles. The manganese dioxide particles having such features can be manufactured by reacting manganese sulfate with sodium peroxodisulfate in an aqueous solution. The process can be controlled to yield high density manganese dioxide. The manganese dioxide formed in the process can be deposited directly onto the surface of electrolytic manganese dioxide (EMD). The manganese dioxide product is particularly suitable for use as a cathode active material in electrochemical cells.Type: GrantFiled: May 22, 1995Date of Patent: July 2, 1996Assignee: Duracell Inc.Inventors: Enoch I. Wang, William L. Bowden, Lifun Lin
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Patent number: 5532085Abstract: The invention relates to alkaline cells containing manganese dioxide cathode active material. A substance selected from the group of compounds CaWO.sub.4, MgTiO.sub.3, BaTiO.sub.3, CaTiO.sub.3, ZnMn.sub.2 O.sub.4, and Bi.sub.12 TiO.sub.20 is added to the cathode of conventional alkaline cells typically having an anode comprising zinc and cathode comprising manganese dioxide and an alkaline electrolyte. The additive increases the service life of the cell.Type: GrantFiled: August 22, 1995Date of Patent: July 2, 1996Assignee: Duracell Inc.Inventors: Stuart M. Davis, Christopher P. Haines, Alexander A. Leef, Peter R. Moses
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Patent number: 5532081Abstract: A metal support disk for an electrochemical cell seal exerts a resilient outward radial force against the seal to maintain seal integrity over a wide range of operating temperature and, at the same time, exerts an upward force against the bottom of the metal end cap terminal of the cell to assure electrical contact between the anode inside the cell and the terminal. The disk includes a central, circular platform connected to an outer, sealing edge sealing flange by an annular flexure means which permits radially inward and outward movement of the sealing edge when the end of the cell is radially crimped during the sealing process. The crimping also moves the central portion of the disk up which results in the upward force being exerted against the end terminal. The flexure means is a sequential series of three annular, curved fibs with the first and third curved downward and the second curved upward.Type: GrantFiled: August 24, 1994Date of Patent: July 2, 1996Assignee: Duracell Inc.Inventors: Christopher L. DePalma, Peter J. Pope, Sean A. Sargeant, Marian Wiacek, Robert A. Yoppolo
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Patent number: 5516604Abstract: The invention relates to alkaline cells containing manganese dioxide cathode active material. A substance selected from the group of compounds Bi.sub.2 O.sub.3, PbO.sub.2, SnO.sub.2, Co.sub.3 O.sub.4, CoO, Bi.sub.2 O.sub.3.3ZrO.sub.3 and K.sub.2 Cr.sub.2 O.sub.7 is added to the cathode of conventional alkaline cells typically having an anode comprising zinc and cathode comprising manganese dioxide and an alkaline electrolyte. The additive increases the specific capacity (amp-hr/g) of the manganese dioxide in the cathode.Type: GrantFiled: February 13, 1995Date of Patent: May 14, 1996Assignee: Duracell Inc.Inventors: Jola E. Mieczkowska, Martin W. Howard
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Patent number: 5385630Abstract: N.sub.2 implantation is used to increase the etch rate of a sacrificial oxide (sometimes referred to as the first gate oxide) in integrated circuitry. This implantation allows etching selectivity by changing the relative etch rates of materials. In the specific implementation described, a field oxide is also provided and this implantation increases the etch rate of the sacrificial oxide relative to that of the field oxide. No heat treatment is applied to the implanted material prior to etching having the ability to repair the damage caused by the bombardment.Type: GrantFiled: June 29, 1993Date of Patent: January 31, 1995Assignee: Digital Equipment CorporationInventors: Ara Philipossian, Hamid R. Soleimani, Brian S. Doyle
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Patent number: 5382831Abstract: For enhanced resistance to electromigration failure, a thin metal film interconnect on an integrated circuit chip should use multiple parallel minimum-width lines when the minimum linewidth is less than one and one-half times the mean grain size of the metal film. When the interconnect is longer than a certain predetermined length, then the multiple lines of the interconnect should have intermediate interconnections or bridges between neighboring ones of the multiple lines. When the interconnect is many times longer than the predetermined length, then the bridges define slots between the neighboring lines, and the slots should have a length of about the predetermined length. When the interconnect is many times longer than the predetermined length and the interconnect has more than two parallel lines, then the slots on one side of a parallel line should be staggered or offset with respect to the slots on the other side of the parallel line.Type: GrantFiled: December 14, 1992Date of Patent: January 17, 1995Assignee: Digital Equipment CorporationInventors: Eugenia M. Atakov, John J. Clement, Brian C. Lee
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Patent number: 5378945Abstract: A voltage level conversion buffer circuit including a first and a second transistor each having a gate, a drain, and a source. The drain of the first transistor and the gate of the second transistor are connected together to provide an input to the buffer circuit, and the gate of the first transistor and the drain of the second transistor are connected to a supply voltage. The sources of the first and second transistors are connected together to provide an output for the buffer circuit.Type: GrantFiled: July 26, 1993Date of Patent: January 3, 1995Assignee: Digital Equipment CorporationInventors: Hamid Partovi, Steven W. Butler, Laun Q. Tran
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Patent number: 5365476Abstract: A three-port Josephson memory cell has one input port (a data line) and two output ports (first and second sense lines). The memory cell receives a write enable pulse on a write line to store a bit of data from the data line as circulating supercurrent. The memory cell also receives a first read enable pulse on a first read line to enable assertion of the stored data onto the first sense line, and receives a second read enable pulse on a second read line to enable assertion of the stored data onto the second sense line.Type: GrantFiled: February 26, 1993Date of Patent: November 15, 1994Assignee: Digital Equipment CorporationInventor: Oleg A. Mukhanov
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Patent number: 5356828Abstract: A method of forming micro-trench isolation regions with a separation of 0.20 .mu.m to 0.35 .mu.m in the fabrication of semiconductor devices involves forming an silicon dioxide layer on select locations of a semiconductor substrate and depositing a polysilicon layer onto the silicon dioxide layer. A layer of photoresist is then deposited over select areas of the polysilicon layer and patterned to form micro-trench isolation regions of widths between about 0.2 .mu.m to about 0.5 .mu.m and aspect ratio of between about 2:1 to about 7:1. Thereafter, the isolation regions are etched for a time and pressure sufficient to form micro-trenches in the substrate surface. The micro-trenches will generally have a width ranging from about 1000 .ANG. to about 3500 .ANG. and depth ranging from about 500 .ANG. to about 5000 .ANG.. The layer of photoresist is then removed to expose the polysilicon layer and a channel stop implant is deposited and aligned with the micro-trenches.Type: GrantFiled: July 1, 1993Date of Patent: October 18, 1994Assignee: Digital Equipment CorporationInventors: Stephen W. Swan, Ellen G. Piccioli
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Patent number: 5346584Abstract: Disclosed is a method of planarizing the surface of a silicon wafer in integrated circuit manufacture where trench isolation techniques are employed. The trenches and active areas on a semiconductor substrate are conformally coated with a layer of silicon oxide. A layer of patterned polysilicon then is deposited on top of the oxide and etched to create filler blocks in depressions above the trenches. Next, the polysilicon is annealed to thereby fill the trenches with an expanded oxide block. The resulting relatively planar surface then is polished back to the nitride cap, to thereby produce a high degree of planarity across all trench and active area dimensions.Type: GrantFiled: July 28, 1993Date of Patent: September 13, 1994Assignee: Digital Equipment CorporationInventors: Andre I. Nasr, Steven S. Cooperman
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Patent number: 5330920Abstract: A method of controlling gate oxide thickness in the fabrication of semiconductor devices wherein a sacrificial gate oxide layer is formed on a semiconductor substrate surface. Nitrogens ions are implanted into select locations of the substrate through the sacrificial gate oxide layer, and the substrate and the gate oxide layer are then thermally annealed. The sacrificial gate oxide layer is then removed and a gate oxide layer is then formed on the substrate layer wherein the portion of the gate oxide layer formed on the nitrogen ion implanted portion of the substrate is thinner than the portion of the gate oxide layer formed on the non-nitrogen ion implanted portion.Type: GrantFiled: June 15, 1993Date of Patent: July 19, 1994Assignee: Digital Equipment CorporationInventors: Hamid R. Soleimani, Brian S. Doyle, Ara Philipossian
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Patent number: 5316965Abstract: An improved process for planarizing an isolation barrier in the fabrication of a semiconductor chip involves reducing the etch rate of the field oxide independently of the sacrificial oxide layer. The field oxide layer is implanted with nitrogen ions and then thermally annealed resulting in a hardened and densified field oxide. In subsequent operations, a sacrificial oxide layer is formed on the semiconductor top surface by thermal oxidation. Upon etching with HF, the etch rate of the hardened field oxide is significantly reduced relative to untreated field oxide. Thus, the exposed hardened field oxide is etched at about the same rate as the sacrificial oxide layer. In the example given, the etch rate of untreated densified TEOS field oxide in 10:1 HF is 6.90 .ANG./sec, while the etch rate of TEOS field oxide hardened according to the processes of this invention is 5.90 .ANG./sec. After planarization using the hardened field oxide, depressions in the isolation barrier are eliminated.Type: GrantFiled: July 29, 1993Date of Patent: May 31, 1994Assignee: Digital Equipment CorporationInventors: Ara Philipossian, Hamid R. Soleimani, Brian S. Doyle
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Patent number: 4771086Abstract: Finely divided water insoluble solid particles free of ionic charges and ranging in size from about 0.01 to several hundred microns or higher, including but not limited to paint pigment particles, are given a generally uniform polymeric encapsulation by admixing such particles in an aqueous reaction medium with a water insoluble monomer polymerizable to form a generally water insoluble polymer free of ionic charges in the presence of a nonionic surface active stabilizing agent, preferably a polyethoxylated alkyl phenol containing at least about eight carbon atoms in the alkyl group thereof and preferably at least about 40-50 ethylene oxide groups per molecule, and polymerization of the monomer is then initiated, usually with heating, with a redox polymerization initiating system which is free of ionic groups and does not decompose to release ionic groups in the reaction medium.Type: GrantFiled: August 22, 1986Date of Patent: September 13, 1988Assignee: Union Carbide CorporationInventor: Robert W. Martin