Abstract: A VSLI chip is implemented with registers which log permanent and intermittent errors occurring within the chip as sensed by concurrent error detection circuitry (CED). If a fatal error is detected (one which would destroy the reliability of chip operations), then the chip is immobilized into a hold mode (freeze). Interrupts are signalled to a cooperating maintenance controller which can pass the error information to an external computer for display and for locating a faulty area.

Abstract: A voltage regulator particularly adapted to A.C. distributed power systems requiring independent voltage regulation at a plurality of frequency responsive power supply modules energized by a power source at a common alternating frequency is provided by resonant tuning of the regulator circuit. An LC resonant circuit determines the operating frequency of the regulator, and may be operated above or below the excitation frequency. The output voltage is applied to a current amplifier which energizes a linearly variable inductor in accordance with the sensed D.C. output voltage. Changes in the output voltage result in changes in the tuned frequency of the LC circuit and the corresponding corrective change in the output voltage. Circuits providing both voltage and current regulation are described.

Abstract: An optical light conducting fiber that has a D-shaped stress sensitive coating of PVF.sub.2 which covers substantially equal length segments of said fiber, so that each of said segments is separated by equal uncoated segments of substantially the same length as said coated segments. The fiber when used in an interferometer provides an antenna that is capable of sensing electromagnetic and other stress-inducting waves in the environment. The optical fiber is polarized by winding it on a specially designed spool, heating it and applying a high intensity electric field in the desired direction.

Abstract: A cache buffer for a multiprocessor system utilizes two RAMs to store validity bits. Use of these RAMs greatly reduces chip area required to implement the validity buffer and reduces interconnection foil (printed connectors) and hence propagation time. An initial clear state is written into all of the memory locations of both RAMs. One of the RAMs then becomes the active validity bit RAM and the other a standby. When a fast invalidate command is received, upon an invalidate parity error indication from a memory readout, for example, the standby RAM is switched to the active RAM, and the validity bits of the formerly active RAM are cleared in sequential write cycles after it is switched to a standby state.

Abstract: A frame building procedure for use in time division multiplexer systems for building a frame with N slots numbered #1, #2, #3, . . . #N in increasing time order. A slot assignment sequence is generated in successive iterations I by initially assigning slot #1 as the first assignment in the sequence. N/2.sup.I is added to the slot numbers of all previously assigned slots during each iteration. Additionally, during each iteration, I is incremented by unity. The iterations are performed until all N slots are assigned when N/2.sup.I =1.

Abstract: An error correcting check of a memory system is provided when a memory in which the Dynamic Random Access Memory (DRAM) is of the type which has input lines that are directly coupled to its output lines. Utilizing this type of DRAM, the memory system employs controls, input, output and read circuitry to read bits out of the memory via the output circuitry and write circuitry to write bits into the memory via the input circuitry. An error checking and correction circuit is coupled to the output means which includes a check bit generator and a syndrome generator, and a control means energizes the error checking and correcting means during the write cycle, as well as the read cycle, so that the errors are detected during the write cycle as well as the read cycle. In this manner, errors which occur in circuitry other than the memory, which includes the memory driving and reading logic and also the check bit generator logic translators and syndrome generators, may be separately detected from memory errors.

Abstract: High speed computing apparatus for performing real time data compression of analog voice data or digital data to be transmitted over a data link. The incoming data stream is divided into blocks of digital data and the blocks are subdivided into digital samples or elements to be compressed. Each sample is analyzed individually to determine its estimated variance and the marginal return to be gained by alloting the sample one or more of the bits to be employed to define the block of digital data. The bits are assigned samples having the highest estimated variance factor so that an optimum allocation of bits to individual samples is achieved with variable ratio data compression. The allocated bits are employed to encode the samples during real time data compression and transmission.

Abstract: Transmitting and receiving apparatus for transmitting data which includes a purged extended Golay (22,7) code encoder at the transmitter for encoding digital data into constant weight unbalanced codewords representative of the digital data. The constant weight unbalanced codewords contain error correction bits and are preferably transmitted as balanced codewords. When the receiver decodes the original digital data, improved tracking and acquisition of the transmitted data is achieved.

Abstract: A dual priority hold register enables the transfer of data to memory ports having serial priority in accordance with two stages of priority. First, all latches of a high priority sector of the register are cleared. Then, the highest priority latch of the low priority sector of the register is cleared, while the latches of the higher priority register are loaded with further data. Following clearance of the low priority latch, all latches of the higher priority register are cleared once again, followed by clearance of the next highest priority latch of the lower priority register sector while the higher priority register is loaded once again. The sequence is repeated until both the higher and lower priority sectors of the register are clear.

Abstract: A system for detecting and isolating fault conditions occurring within a digital electronic system. The digital electronic system includes a first digital logic array for generating digital outputs in response to a set of digital signal inputs applied to it. The digital logic array is replicated and the second array is configured to receive the same inputs as the first. The first and second arrays are made to operate in synchrony so as to normally produce identical outputs in the absence of fault conditions occurring either in the first or second array or in the inputs applied to them. The digital outputs from the first array are applied to first and second residue code generators having different modulii. Likewise, the outputs from the second arry are applied to third and fourth residue code generators which are identical in make-up to the first and second residue code generators.

Abstract: A regulator circuit for equalizing the load currents of a plurality of power supply modules connected in common to feed a common load. Each of the modules includes a pulse-width modulator for adjusting the duty cycle of the module, thereby to adjust the voltage regulation point and corresponding current output of the module. A current sensor produces a current level signal proportional to the current output of the module. The current level signal is applied through a current amplifier to generate a corresponding variable error voltage. A fixed reference voltage derived from the output voltage and the variable error voltage are applied to the pulse-width modulator to vary the duty cycle so as to produce a decrease in load voltage with an increase in current output and an increase in the load voltage with a decrease in current output thereby equalizing the current output of the module with modules having substantially equal output voltages.

Abstract: An electro-mechanical probe is comprised of a thin flat ring-shaped frame, and an elastic transparent membrane which is attached to a downward-facing surface of the ring-shaped frame and which traverses the aperture of the ring. On this membrane are a plurality of microscopic conductive bumps which are aligned with and which are outside of the aperture of the ring. Also integrated into the membrane are a plurality of microscopic conductors, and they serve as a means for sending electrical signals to and receiving electrical signals from the bumps. In operation, the probe frame is fitted with a cover which overlies the elastic membrane to thereby form an enclosed chamber. Both the cover and the elastic membrane are transparent so that the bumps on the membrane can be aligned with corresponding contacts on a semiconductor chip or interconnect module which is to be tested.

Abstract: A multibank computer memory system is provided in which the storage banks monitor the initiate line while each bank operation is being processed to verify that another initiate is not received before it can be processed. This serves to check that the control logic is not in error, and that there is no error between the control section and the banks.

Abstract: A method for internal self-testing is provided for a VLSI chip having gates, logic, registers, memory circuitry, etc. The registers are connected into a shift chain circuit form. A set of control flip-flops operate to convert the registers to multifunction shift registers (MFSR's) which operate as flip-flops during a test cycle and as latches during normal operations. Selected MFSR's function to generate test patterns to the chip circuitry which have output signals to an output MFSR which collects a signature that can be compared to a predetermined signature to determine error-free or error-incurred operation of the VLSI circuitry.

Abstract: A failure detection system for variable field partial write system for merging data bits in a memory word upon programmable request is described. The variable bit field can be selected for any number of bit positions from a single bit up to and including a full data word, where data words are comprised of a predetermined number of bytes each containing a predetermined number of bits. A Start Bit Code defines the location of the start of the bit field to be written and an End Bit Code defines the bit after the last bit that is to be merged and written. Write and Read Data to be used in the partial merge operation are stored in a Merge Register along with a code derived from the Start and End Code bits. The bits not used are stored in a Non-Merge Register. Parities are compared to verify that a parity error did not occur when the Merge Register was loaded.

Abstract: Apparatus is provided for locking onto a severe doppler shifted data modulated carrier signal. A phase lock loop of the type having a data detection branch, a carrier tracking branch and a voltage controlled oscillator branch is modified to provide a summing circuit at the input of the voltage control oscillator in the voltage controlled oscillator branch. A sweep control circuit is connected to the input of the summing circuit for sweeping the voltage controlled oscillator through a range of frequencies which encompass the doppler shifted carrier frequency. An automatic frequency control circuit is connected to the input of the summing circuit for automatically disconnecting the sweep control circuit from the summing circuit when the frequency of the voltage controlled oscillator reaches a predetermined value defining a window which encompasses only the center frequency of the doppler shifted carrier frequency.

Abstract: A protective package unit for shipping printed circuit boards provides an outer container into which one or more printed circuit boards can cushionably reside while encompassed in a see-through bag providing protection from electromagnetic radiation and electrostatic discharge.

Abstract: An integrated circuit having improved planarity includes a substrate, a plurality of transistors integrated into a top surface of the substrate, and a plurality of insulating layers over the top surface which are interleaved with respective sets of signal conductors. These signal conductors are spaced apart on the insulating layers and are routed through holes in the insulating layers to the transistors in order to carry signals to and from the transistors. Also, in accordance with the invention, the integrated circuit further includes dummy conductors on the insulating layers in the spaces between the signal conductors. These dummy conductors are open circuited and consequently carry no signals. Their function is purely mechanical; and specifically, they function to partially fill the spaces between the signal conductors such that an overlying insulating layer can be formed without peaks and valleys.

Abstract: A speed-up circuit is employed in a semiconductor chip of the type that includes a P-type substrate with a plurality of NPN transistors integrated into a surface thereof. Those transistors include a first NPN transistor having a base which receives a control signal, a collector coupled to a voltage bus, and an emitter which drives a first resistor plus a base of a second NPN transistor plus a small parasitic capacitance. The second NPN transistor has a collector coupled to a voltage bus, and an emitter which drives a second resistor plus a larger parasitic capacitance. And, the speed-up circuit is comprised of: a PNP transistor having an emitter coupled to the large capacitance, a base coupled to a tap on the first resistor, and a collector coupled to the substrate.

Abstract: An improved interface arrangement between an antenna controller and one or more antennas. The interface includes a reduced number of control lines but is capable of handling complete interface requirements including control and status between the antenna controller and the antenna.