Abstract: Method and apparatus for drawing vectors on limited precision display devices in amounts of time approximately proportional to the vector's geometric length. Vectors are drawn by a series of strokes. Each stroke is a series of counter control signals, each signal representing a vertical, horizontal, or diagonal movement of the CRT electron beam between adjacent addressable screen points. The counter control signals making up the strokes are stored on a look-up table.

Abstract: A predictive time base control circuit for a waveform sampling system of the type which converts a sequence of analog waveform samples into a sequence of digital quantities for storage in an addressable acquisition memory. The time base circuit generates a sampling control signal which initiates sampling at the end of a time interval of programmable duration following detection of a triggering event in the waveform, and which maintains sampling thereafter at regular intervals. The time base circuit permits the sampling system to operate in an equivalent time mode in which repetitive waveform sections are sampled at progressively skewed sampling intervals with respect to a repetitive triggering event. The sampling control signal is also frequency divided, delayed, and then applied as a write control signal to the sampling system acquisition memory.

Abstract: An apparatus for generating trigger signals responsive to a selected pattern of event detection signals, the apparatus comprising an interim function bus, programmable means to selectively energize conductors of the interim function bus on detection of the selected event detection signal pattern, and programmable means to generate the trigger signal on detection of a selected pattern of interim function bus signals. The generating means are programmed for pattern recognition by binary data appearing on control lines from a shift register, the shift register being loaded by serial data from external control circuits. The apparatus also includes provisions for synchronizing the generation of signal patterns on the interim function bus to a system clock, and for synchronizing the generation of trigger signals to clocks associated with triggerable devices.

Abstract: A method and apparatus are disclosed which provide for the removal of distortion present in a digital output signal from a linear analog signal processing system. Two applications are disclosed: digital compensation and digital equalization. Digital compensation provides for the removal of distortion from a single signal processing system. In particular, an adaptive digital filter operates to provide processing of an output signal from the signal processing system in accordance with correction criteria determined by a controller in response to a training signal. Digital equalization is employed with respect to a plurality of signal processing systems, and provides equalization of an output signal from one signal processing system in accordance with characteristics of a selected signal processing system.

Abstract: A method and apparatus for securing enlongatge members of generally cylindrical form in end-to-end relationship, particularly for forming an optic fiber splice. Optic fibers are spliced by pressing a form, preferably an optic fiber of the same diameter as those to be spliced, into a deformable body to create a groove for receiving the ends of the optic fibers in close alignment. To secure the optic fibers, an index matching adhesive is cured by UV irradiation through a glass cover plate bonded to the deformable body.

Abstract: A hand-held inertial mouse provides input data to a computer from which the computer can determine the translational and angular displacement of the mouse. The mouse includes accelerometers for producing output signals of magnitudes proportional to the translational acceleration of the mouse in three non-parallel directions. Pairs of these accelerometers are positioned to detect acceleration along each axis of a cartesian coordinate system such that an angular acceleration of the mouse about any axis of rotation causes representative differences in the magnitudes of the output signals of one or more of these accelerometer pairs. The translational velocity and displacement of the mouse is determined by integrating the accelerometer output signals and the angular velocity and displacement of the mouse is determined by integrating the difference between the output signals of the accelerometer pairs.

Abstract: A color graphic display system has self-test capability for testing system elements between the frame buffer and the display monitor inputs. The DAC output analog signals are converted to a digital signal and processed to provide an output test bit, which is input to the graphics processor. Additional self-test hardware includes address and data lines from the graphics processor to the color map for directly loading test bit patterns into the color map. The system self-tests the frame buffer, shift registers and DACs by loading various predetermined test bit patterns into the frame buffer and the color map; cycling that data through the display system; reading the test bit; comparing the output test bit values to expected values; and reporting any errors detected. The system also includes a method for self-testing the refresh counter address path into the frame buffer.

Abstract: A bus arbitration controller controls access of a plurality of asynchronous potential master devices to a unitary interconnecting bus by forming a distributed state machine of arbitration logic units in each of the potential master devices. Each arbitration logic unit receives control signals by way of the unitary bus which are common to all the devices, each control signal being the logical OR of the corresponding signals from all other devices. The control signals include a device address/priority number and a synchronization signal set. The arbitration logic includes a priority resolver which awards bus access to a device having the highest address/priority number, and control logic which receives the common synchronization signal set and synchronizes the operation of the device in which the arbitration logic resides with all other devices contending for the unitary bus. The control logic and the priority resolver are programmable array logic circuits.

Abstract: An automatic picture coding system including a method for converting a bit-map image of the picture to vectors as the picture is being scanned. The bit map is delayed as it is being generated to form a series of tessellations or windows of data. The windows are propagated through a series of neighborhood-logic elements which perform data transformation operations such as growing, smoothing and thinning of the bit-map image. A bit stream output from the neighborhood logic which output includes only line and edge features of the original picture is transferred serially to a microcomputer where the features are partitioned into a plurality of line segments. Each line segment is chain coded and temporarily stored, as it is acquired, in a corresponding one of a plurality of lists, the lists being linked in an order corresponding with the order in which the segments are acquired.

Abstract: An optical phase shifter comprises an optical waveguide of electro-optic material and an electrode structure associated with the waveguide for imposing an electrical field on the waveguide. The electrode structure comprises at least two groups of electrodes, each group having at least first and second electrodes between which the waveguide passes. The first electrode of one group and the second electrode of the other group are on opposite respective sides of the waveguide and are connected to respective input terminals for receiving an electrical signal. The second electrode of the one group is connected to the first electrode of the other group.

Abstract: An analog-to-digital converter (10) comprises a set of comparators (12a-12f) for providing a set of different output signals whose logic states are a function of an analog input signal voltage and one or more reference voltage signals supplied by a resistive network (16). The comparators are connected to a decoder (20) for processing the thermometer code outputs of the comparators to generate a digital word output corresponding to the voltage amplitude of the analog signal. Several of the comparators are also connected to an error checking network (22), including a preconditioning circuit (100) and a detection circuit (102) for processing these comparator outputs to provide an error signal whenever one or more of the comparators are not operating properly. The error checking network and decoder are connected to an error correction circuit (26) for correcting the digital word signal in accordance with the error signal.

Abstract: Information for a histogram is provided through generation of a pseudo-random sequence in a shift register connected in predetermined feedback relation. A histogram element storage location is addressed in a random access memory and is used for loading the shift register in parallel when an event corresponding to that element takes place. The shift register proceeds from that point to increment a pseudo-random sequence for the duration of the event, and the concluding value of the sequence is loaded back into the random access memory location at the conclusion of the event. A network between the random access memory and the shift register loads the shift register with a pattern that replicates the pattern that would exist in the shift register if the shift register had already been loaded and the data therein was shifted once.

Abstract: A method and apparatus is disclosed for the improved monitoring and detection of improper device operation. Operation of a prototype device is first modeled. In particular, a set of test vectors is selected to provide a desired degree of testing of the prototype unit. The expected response of the prototype to the selected set of test vectors is determined through the use of analytical prediction means, and stored for subsequent comparison with the operation of the prototype unit. Thereafter, the selected set of test vectors are applied to the prototype unit, and the response thereto compared in real time with the expected responses. Improper operation of the prototype device is thereby identified, and associate information recorded for subsequent analysis.

Abstract: A method and circuit employ digital techniques in processing an input signal of a first frequency to develop an output signal of a second frequency that is a multiple of the first frequency. During each cycle of the input signal, a presettable down counter (146) is decremented from its maximum value at a rate of 1/T.sub.1. The digital word appearing at the output of the down counter at the end of the cycle is programmed into an up counter (278) that is clocked at a rate of 1/T.sub.2. The frequency of the signal developed at the overflow output (336) of the up counter is divided by two by a flip-flop (342) whose output (348) provides a signal of a frequency which is T.sub.1 /2T.sub.2 times that of the input signal. The frequency of the output signal changes after one cycle of a change in frequency of the input signal. The frequency multiplication factor can be a noninteger value.

Abstract: For a computer system having peripheral devices coupled to a common bus through interface devices transmitting and receiving messages containing an address code matching a stored address code, a dynamic address assignment system stores a unique address code in each interface device following system startup. On system start up each interface device stores a type number and an adjustable serial number, type numbers for peripheral devices of the same type being identical while serial numbers for all peripheral devices of the same type are adjusted to different values. A master controller transmits to all peripheral devices a series of universally addressed count commands. Each interface device counts the count commands and, when the count reaches a poll number determined by the unique combination of stored type and serial numbers, requests and obtains a unique address code from the host computer.

Abstract: In a color graphics display system, video analog self-test hardware for testing the system elements between the frame buffer and the CRT display monitor is provided including a bi-directional data bus between the graphics processor and the color map, an analog comparator, an integrator, and an analog multiplexor. The self-test method includes calibrating the self-test circuitry with respect to a reference voltage. The method next includes testing the DACs by outputting predetermined bit patterns to each of the DACs via the frame buffer, measuring each DAC output level in response to each input bit pattern, comparing the DAC output levels to predetermined limits, and reporting the results. Provision is made also for testing the system clock.

Abstract: A digitizer system includes M digitizers, each producing a separate waveform data sequence representing a succession of instantaneous magnitudes of an input signal at sample times determined by a periodic clock signal. Transmission of the clock signal to each digitizer is delayed by a corresponding adjustable delay time so as to control the relative sample timing of the digitizers. To adjust sample timing, a sine wave signal is applied as the input signal to each digitizer such that the M digitizers produce M separate waveform data sequences in response to said input signal and the M data sequences are interleaved and windowed to form a single waveform data sequence. A first sequence of complex numbers representing a discrete Fourier transform of the single waveform data sequence is generated and then a second sequence of M complex numbers is formed from elements corresponding to relative magnitude peaks of the first sequence.

Abstract: An apparatus for displaying the display outputs of a plurality of simultaneously active computer processes in corresponding windows on a single screen includes a microcomputer, a display screen and display system software. The software represents a plurality of virtual terminals, one corresponding to each active process, for emulating the operation of real terminals communicating with the processes. Each virtual terminal maintains a display list comprising a set of instructions defining a display on a screen according to the output from the corresponding process. The software also includes a screen process for maintaining a subrectangle list comprising a set of instructions for allocating window portions of the screen to the displays defined by the separate display lists. A display list processor is provided for creating the windows on the screen according to the display and subrectangle lists.

Abstract: A cathode-ray tube has at least two mounting members that are angularly spaced about the axis of the CRT, and a support structure for receiving the CRT has mounting members for engagement with the mounting members of the CRT, whereby the CRT and the support structure have at least first and second pairs of mutually interengageable mounting members. The first pair of mounting members comprises a first cylindrical post and a circular hole for receiving the first post and the second pair of mounting members comprises a second cylindrical post and a slot having a width substantially equal to the diameter of the second post.

Abstract: A probe body for a measurement system comprises a probe-tip terminal for connection by way of a probe tip to a test point, a cable port for connection by way of at least one cable to a measurement instrument, probe circuitry, a function generator, and a switch. In a first state of the switch, the input terminal of the probe circuitry is connected to the probe-tip terminal and in a second state of the switch the input terminal of the probe circuitry is connected to the function generator. When the switch is in the second state, the function generator may be used to impress a signal having a predetermined waveform on the probe circuitry.