Patents Represented by Attorney, Agent or Law Firm Roberts & Mercanti, LLP
  • Patent number: 6831005
    Abstract: A process for the formation of structures in microelectronic devices such as integrated circuit devices. Vias, interconnect metallization and wiring lines are formed using single and dual damascene techniques wherein dielectric layers are treated with a wide electron beam exposure.
    Type: Grant
    Filed: October 17, 2000
    Date of Patent: December 14, 2004
    Assignee: Allied Signal, Inc.
    Inventor: Matthew F. Ross
  • Patent number: 6682350
    Abstract: A laser pistol and a method or system for retrofitting sharpshooting pistols whose recoil mechanism is complicated in design and has an unrealistic trigger resistance. A conversion of known sharpshooting pistols into simulation-type laser pistols, whose mechanism has a realistic trigger resistance and a corresponding recoil, and their simple reconversion is provided.
    Type: Grant
    Filed: May 31, 2002
    Date of Patent: January 27, 2004
    Inventors: Hermann Kehl, Alfred De Vries
  • Patent number: 6670022
    Abstract: The present invention relates to nanoporous dielectric films and to a process for their manufacture. A substrate having a plurality of raised lines on its surface is provided with a relatively high porosity, low dielectric constant, silicon containing polymer composition positioned between the raised lines and a relatively low porosity, high dielectric constant, silicon containing composition positioned on the lines.
    Type: Grant
    Filed: November 3, 2000
    Date of Patent: December 30, 2003
    Assignee: Honeywell International, Inc.
    Inventors: Stephen Wallace, Douglas M. Smith, Teresa Ramos, Kevin H. Rodrick, James S. Drage
  • Patent number: 6660406
    Abstract: There are provided an electrodeposited copper foil with carrier that can be used for manufacturing a printed wiring board that excels in the finished accuracy of the resistor circuit in comparison with a conventional printed wiring board with resistor circuits, and a method for manufacturing such a printed wiring board with resistor circuits.
    Type: Grant
    Filed: June 20, 2001
    Date of Patent: December 9, 2003
    Assignee: Mitsui Mining & Smelting Co., Ltd.
    Inventors: Takuya Yamamoto, Takashi Kataoka, Naotomi Takahashi
  • Patent number: 6657849
    Abstract: A capacitor, which has a pair of conductive foils each having a dielectric layer on its surface, wherein the dielectric layers are attached to one another. In one process for its production, a capacitor is formed by applying a first dielectric layer onto a surface of a first conductive foil; applying a second dielectric layer onto a surface of a second conductive foil; and then attaching the first and second dielectric layers to one another. The resulting capacitor exhibits excellent void resistance.
    Type: Grant
    Filed: August 24, 2000
    Date of Patent: December 2, 2003
    Assignee: Oak-Mitsui, Inc.
    Inventors: John A. Andresakis, Edward C. Skorupski, Scott Zimmerman, Gordon Smith
  • Patent number: 6652922
    Abstract: An improved method for producing substrates coated with dielectric films for use in microelectronic applications wherein the films are processed by exposing the coated substrate surfaces to a flux of electron beam. Substrates cured via electron beam exposure possess superior dielectric properties, density, uniformity, thermal stability, and oxygen stability.
    Type: Grant
    Filed: May 23, 1996
    Date of Patent: November 25, 2003
    Assignee: Alliedsignal Inc.
    Inventors: Lynn Forester, Neil H. Hendricks, Dong-Kyu Choi
  • Patent number: 6629348
    Abstract: The invention relates to the manufacture of printed circuit boards having improved interlayer adhesion. More particularly, the present invention pertains to adhesiveless printed circuit boards having excellent thermal performance and useful for producing high-density circuits. A metal foil is laminated to an etched surface of a polyimide substrate having a polyimide film thereon. Etching the substrate surface allows for strong adhesion of a pure polyimide film to the substrate.
    Type: Grant
    Filed: May 1, 2001
    Date of Patent: October 7, 2003
    Assignee: Oak-Mitsui, Inc.
    Inventors: Edward C. Skorupski, Jeffrey T. Gray, John A. Andresakis, Wendy Herrick
  • Patent number: 6610182
    Abstract: The present cup-type plating apparatus improves a conventional cup-type plating apparatus and prevents the surface of a wafer due to a mist of the plating solutions from being contaminated. A plating solution is supplied to a wafer which is placed on a wafer support provided along an opening at the top of a plating tank from a solution-supply port provided at the bottom of the plating tank by an upward-moving stream; the plating solution is made to flow out of a solution-outlet port provided for the plating tank; and plating is performed while the plating solution is brought into contact with a surface of the placed wafer, which is to be plated, wherein the solution-outlet port has a solution-outlet path in which the discharged plating solution is isolated from the outer space.
    Type: Grant
    Filed: June 18, 2001
    Date of Patent: August 26, 2003
    Assignee: Electroplating Engineers of Japan, Limited
    Inventor: Yasuhiko Sakaki
  • Patent number: 6610145
    Abstract: A process for forming a uniform nanoporous dielectric film on a substrate. The process includes horizontally positioning a flat substrate within a cup; depositing a liquid alkoxysilane composition onto the substrate surface; covering the cup such that the substrate is enclosed therein; spinning the covered cup and spreading the alkoxysilane composition evenly on the substrate surface; exposing the alkoxysilane composition to water vapor and base vapor to thereby form a gel; and then curing the gel. The invention also provides an apparatus for spin depositing a liquid coating onto a substrate. The apparatus has a cylindrical cup with an open top section and removable cover which closes the top. A vapor injection port extends through the center of the cover. Suitable means hold a substrate centered within the cup and spin the cup.
    Type: Grant
    Filed: September 19, 2001
    Date of Patent: August 26, 2003
    Assignee: AlliedSignal Inc.
    Inventors: Neil Hendricks, Douglas M. Smith, Teresa Ramos, James Drage
  • Patent number: 6610417
    Abstract: The invention relates to the manufacture of metal foil electrodes useful in the manufacture of printed circuit boards having passive circuit components such as capacitors, resistors or inductors configured in a planar orientation. A copper foil is coated on each opposite side with a thin layer of nickel, which increases the range of functionality of the foil.
    Type: Grant
    Filed: October 4, 2001
    Date of Patent: August 26, 2003
    Assignee: Oak-Mitsui, Inc.
    Inventors: John A. Andresakis, Edward Skorupski, Wendy Herrick, Michael D. Woodry
  • Patent number: 6607794
    Abstract: A light-reflecting article having an average total reflectivity of at least about 93%, e.g., at least about 95%, for light in a 400 to 700 nanometer wavelength range comprises a thermoplastic or thermoset polymer matrix, such as an acrylonitrile-butadiene-styrene-based matrix, in which is dispersed reflective filler particles such as rutile titania and a flame-retardant material. The flame-retardant material may contain a particulate metal oxide synergist, e.g., antimony trioxide or antimony pentoxide, and a quencher such as a brominated organic compound, e.g., bis(tribromophenoxy)ethane. The polymer matrix and filler may be selected so that their respective refractive indices and the size range of the filler particles satisfies a mathematical relationship having as a function thereof the mean freespace (vacuum) wavelength of the light range being reflected.
    Type: Grant
    Filed: January 28, 1999
    Date of Patent: August 19, 2003
    Assignee: AlliedSignal Inc.
    Inventors: John Colvin Wilson, Lawrence Wayne Shacklette
  • Patent number: 6606792
    Abstract: A process for forming printed circuit substrates incorporating impedance elements in which a pattern of impedance elements and a conductor pattern are incorporated on an insulating support. The process involves depositing a layer of an impedance material on a first surface of a sheet of an electrically highly conductive material and attaching a second surface of the sheet of highly conductive material to a support. Then one applies a layer of a photoresist material onto the layer of impedance material with imagewise exposure and development. After etching away the portion of the impedance layer material underlying the removed nonimage areas of the photoresist material, a pattern of impedance elements remain on the sheet of highly conductive material. Thus printed circuit board with impedance elements can be manufactured to a high degree of electrical tolerance.
    Type: Grant
    Filed: May 25, 2000
    Date of Patent: August 19, 2003
    Assignee: Oak-Mitsui, Inc.
    Inventor: John A. Andresakis
  • Patent number: 6607991
    Abstract: An electron beam exposure method is described which provides a means of curing spin-on-glass or spin-on-polymer dielectric material formed on a semiconductor wafer. The dielectric material insulates the conductive metal layer and planarizes the topography in the process of manufacturing multilayered integrated circuits. The method utilizes a large area, uniform electron beam exposure system in a soft vacuum environment. A wafer coated with uncured dielectric material is irradiated with electrons of sufficient energy to penetrate the entire thickness of the dielectric material and is simultaneously heated by infrared heaters. By adjusting the process conditions, such as electron beam total dose and energy, temperature of the wafer, and ambient atmosphere, the properties of the cured dielectric material can be modified.
    Type: Grant
    Filed: December 29, 1999
    Date of Patent: August 19, 2003
    Assignee: Electron Vision Corporation
    Inventors: William R. Livesay, Matthew F. Ross, Anthony L. Rubiales, Heike Thompson, Selmer Wong, Trey Marlowe, Mark Narcy
  • Patent number: 6589889
    Abstract: A process for forming a substantially planarized nanoporous dielectric silica coating on a substrate suitable for preparing a semiconductor device, and semiconductor devices produced by the methods of the invention. The process includes the steps of applying a composition that includes at least one silicon-based dielectric precursor to a substrate, and then, (a) gelling or aging the applied coating, (b) contacting the coating with a planarization object with sufficient pressure to transfer a planar impression to the coating without substantially impairing formation of desired nanometer-scale pore structure, (c) separating the planarized coating from the planarization object, (d) curing said planarized coating; wherein steps (a)-(d) are conducted in any one of the following sequences: (a), (b), (c) and (d); (a), (d), (b) and (c); (b), (a), (d) and (c); and (b), (c), (a) and (d).
    Type: Grant
    Filed: September 9, 1999
    Date of Patent: July 8, 2003
    Assignee: AlliedSignal Inc.
    Inventors: Denis H. Endisch, James S. Drage
  • Patent number: 6589862
    Abstract: The invention relates to cured dielectric films and a process for their manufacture which are useful in the production of integrated circuits. Dual layered dielectric films are produced in which a lower layer comprises a non-silicon containing organic polymer and an upper layer comprises an organic, silicon containing polymer. Such films are useful in the manufacture of microelectronic devices such as integrated circuits (IC's). In one aspect the upper layer silicon containing polymer has less than 40 Mole percent carbon containing substituents, and in another aspect it has at least approximately 40 Mole percent carbon containing substituents.
    Type: Grant
    Filed: February 13, 2002
    Date of Patent: July 8, 2003
    Assignee: AlliedSignal Inc.
    Inventors: Shi-Qing Wang, Jude Dunne, Lisa Figge
  • Patent number: 6582777
    Abstract: A process for forming low dielectric constant dielectric films for the production of microelectronic devices. A dielectric layer is formed on a substrate by chemical vapor depositing a monomeric or oligomeric dielectric precursor in a chemical vapor deposit apparatus, or a reaction product formed from the precursor in the apparatus, onto a substrate, to form a layer on a surface of a substrate. After optionally heating the layer at a sufficient time and temperature to dry the layer, the layer is then exposed to electron beam radiation, for a sufficient time, temperature, electron beam energy and electron beam dose to modify the layer. The electron beam exposing step is conducted by overall exposing the dielectric layer with a wide, large beam of electron beam radiation from a large-area electron beam source.
    Type: Grant
    Filed: February 17, 2000
    Date of Patent: June 24, 2003
    Assignee: Applied Materials Inc.
    Inventors: Matthew Ross, Heike Thompson, Jingjun Yang
  • Patent number: 6583047
    Abstract: A method of forming a microelectronic device while preventing photoresist poisoning. Various layers of conductive metals and dielectric materials are deposited onto a substrate in selective sequence to form an integrated circuit. Vias and trenches are formed throughout the structure by exposing and patterning a photoresist material. The dielectric materials of the insulating layers are protected from the photoresist to prevent chemical reactions which lead to photoresist poisoning. This is done by forming a modified surface layer on the dielectric material by either depositing an additional layer that covers the dielectric material, or by modifying the exposed surface of the dielectric material to a plasma or chemical treatment.
    Type: Grant
    Filed: December 26, 2000
    Date of Patent: June 24, 2003
    Assignee: Honeywell International, Inc.
    Inventors: Brian J. Daniels, Jude A. Dunne, Joseph T. Kennedy
  • Patent number: 6582640
    Abstract: From about 50 to about 90% by weight of fibers, in particular wood fibers, and/or pellets made from cellulose or from wood, are mixed with from about 10 to about 50% by weight of a hot-curing resin, each of the percentages by weight being based on the total weight of the mixture. Instead of a single resin it is also possible to use a mixture made from two or more hot-curing resins. The mixture made from fibers and/or pellets and resin is kneaded and homogenized and then passed on to an extruder which has various heating zones in which the mixture is heated. Care has to be taken here that the maximum temperature, arising at the extruder exit, does not exceed about 120° C., since above this temperature the resin(s) begin(s) to cure.
    Type: Grant
    Filed: February 20, 2001
    Date of Patent: June 24, 2003
    Assignee: Trespa International B.V.
    Inventor: Remco Cornelis Willemse
  • Patent number: 6559045
    Abstract: The invention relates to the formation of structures in microelectronic devices such as integrated circuit devices by means of borderless via architectures in intermetal dielectrics. An integrated circuit structure has a substrate, a layer of a second dielectric material positioned on the substrate and spaced apart metal contacts are on the layer of the second dielectric material. The metal contacts have side walls, and a lining of a first dielectric on the side walls; a space between the linings on adjacent metal contact side walls filled with the second dielectric material, a top surface of each of the metal contacts, the linings and the spaces are at a common level. An additional layer of the second dielectric material is on some of the metal contacts, linings and filled spaces. At least one via extends through the additional layer of the second dielectric material and extends to the top surface of at least one metal contact and optionally at least one of the linings.
    Type: Grant
    Filed: June 12, 2002
    Date of Patent: May 6, 2003
    Assignee: Alliedsignal Inc.
    Inventor: Henry Chung
  • Patent number: D477836
    Type: Grant
    Filed: October 24, 2002
    Date of Patent: July 29, 2003
    Assignee: Royal Consumer Information Products, Inc.
    Inventors: James R. Balog, Timothy C. Repp