Abstract: A method and apparatus for carrying out synchronous co-division multiple access (SCDMA) communication of multiple channels of digital data over a shared transmission media such as a cable television system coaxial cable, a fiber optic or copper conductor telephone link, terrestial microwave, satellite link, local or wide area network, wireless including cellur network or some combination of these media using suitable interface circuitry. The system includes modems at remote units and a central unit to receive time division multiplexed digital data arranged into timeslots or channels and uses orthogonal codes to encode each channel of multiple data and spread the energy of each channel data over a frame of data transmitted in the code domain. Spreading the data this way makes the system less susceptible to impulse noise.

Abstract: The spreader comprises an elongated hopper which is mountable across the rear end of a truck box in an underslung fashion. When the end-gate of the box is opened, aggregate can spill into the hopper. The hopper forms a discharge slot along its lower end. A pair of coaxial, end-to-end drums are rotatably mounted in the hopper and extend into the lower portion of the slot. Each drum is separately driven. A ramp extends between the box floor and the front upper quadrants of the drums for feeding aggregate thereto. A pair of separately actuated, pivoting flaps bear against the upper rear quadrants of the drums and function to open or close the upper portion of the slot. The ramp/drum assembly provides even, well distributed discharge of aggregate. The flap/drum assemblies can provide an effective shut-off or lay down narrow or wide strips of aggregate.

Abstract: This disclosure is directed to novel systems and methods for producing motion in response to a drive signal where the motion has a smooth translational reversal. The system accepts a command position signal and compares the command position signal to the actual position of a linear actuator to develop a position error that is then conditioned to produce a pair of valve drive signals that command series connected proportional valves that supply the linear actuator from a common connection of the valves with fluid flow and pressure to adjust the position of the linear actuator so as to reduce the position error by imparting motion to the linear actuator, thus imparting motion to a load. The conditioning of the valve drive signals includes the processing of the position error and the application of a quiescent drive signal to develop or nearly develop a quiescent fluid flow through the series connected valves. The quiescent drive signal can be automatically or manually developed.

Abstract: An interface circuit for use in the layout of padframe interface circuits for field programmable gate arrays having a plurality of I/O cells each of which may be programmed as an input or an output (or both) and a programmable connection matrix which provide programmable pathways between the data output signals generated by the core array of logic blocks and I/O cells programmed as outputs and provide programmable pathways between I/O cells programmed as inputs and data input conductors going into the core array. The interface circuits are all substantially identical in structure, and each includes a sufficient number of power and ground connections to supply adequate current to the number of I/O cells the interface has. Each interface circuit also includes at least one and preferably two open spaces into which conductive paths may be laid out to carry power to the core array or carry dedicated signals to circuits other than the core which also reside on the integrated circuit.

Abstract: A source for a linear homodyne transceiver that generates repeated linear chirps. A YIG oscillator with a main coil and an FM coil receives a basic linear current ramp at the main coil to generate a chirp. The FM coil is coupled to receive a PLL error signal. The PLL receives a sample of the output signal from the YIG oscillator at one input and a linear chirp reference signal at the other input generated by a DDS chirp generator. Any variation between the linear chirp frequency at any instant and the actual frequency output by the YIG is corrected by an error signal to the FM coil to correct for nonlinearities of the YIG caused by variations in the chirp rate, the rate of change of frequency per second per chirp, temperature variations and microphonics.

Abstract: A method for repairing a locally damaged, dented surface of a wall, whereby the surface is provided with a relief, as well as a wall comprising a locally repaired surface, which has been repaired by using the method below. A mould comprising an impression of the relief of an undamaged part of the surface is made, the dented surface is filled with a filler, after which the impression on the mould is pressed into the filling material, as a result of which a relief corresponding with the original relief is formed in the filling material.

Abstract: A variety of PC card interfaces to interface from many different types of input devices to Personal Digital Assistants or palmtop computers through PCMCIA slots. The disclosed interfaces can receive data in undecoded format from laser based, wand based or CCD based barcode scanning engines, decode the data to alphanumeric characters and pass the decoded data to the PDA via the PCMCIA 68 pin bus. Other PC card based interfaces are also disclosed which can accept input data in the form of ASCII or EBCDIC characters from virtually any type of input device which a standard serial or parallel output or custom output bus and input that data to the PDA through the PCMCIA bus. Some embodiments use programmed general purpose microprocessors to decode undecoded barcode scan data on the PC card. Other embodiments use custom-programmed, commercially available barcode decoding chips to decode incoming undecoded barcode scan data.

Abstract: A high speed active link switching technology suitable for implementing field programmable gate arrays using current mode logic in the high speed data path, and CMOS steering logic outside the high speed data path to enable the high speed switching logic and to implement multiplexer, selector and crossbar switch functions. High speed emitter follower logic compatible with the high speed switching logic for level shifting, buffering, and providing more current sink or source capacity is also disclosed. An advantage of the active link technology disclosed herein is that the active links do not degrade rise and fall times of high speed data signals nearly as much as the passive links of prior art field programmable gate arrays thereby enabling use of FPGAs in higher speed applications than was previously possible.

Abstract: A license restriction management system having wrapper programs and agents as appropriate to manage launches of application programs in distributed systems of computers having a multiplicity of different operating systems. The system includes passive monitoring where only data regarding launches is collected or active monitoring where the number of copies of licensed programs in execution at any particular time is actively controlled by the agents and wrappers in cooperation with a license restriction management process. Configuration of the agents to use TCP or UDP communication protocols and to do automatic denial of unauthorized applications based upon either locally kept or centrally kept lists of authorized applications.

Abstract: This disclosure is directed to novel systems and methods for displaying an interactive event, such as a race car video game. Numerous display devices are disclosed for displaying video and audio elements of the video game to both current players and to individuals not currently playing the video game. The race car video game further has seating for two occupants, a driver and a crew member and has a separate video monitor for the crew member, through which the crew member can selectively view the race from different viewpoints and can obtain race information. The display of the race car game to individuals not currently playing the game varies according to several factors to enhance the attraction and interest in the race car video game.

Abstract: An interface circuit for use in the layout of padframe interface circuits for field programmable gate arrays having a plurality of I/O cells each of which may be programmed as an input or an output (or both) and a programmable connection matrix which provide programmable pathways between the data output signals generated by the core array of logic blocks and I/O cells programmed as outputs and provide programmable pathways between I/O cells programmed as inputs and data input conductors going into the core array. The interface circuits are all substantially identical in structure, and each includes a sufficient number of power and ground connections to supply adequate current to the number of I/O cells the interface has. Each interface circuit also includes at least one and preferably two open spaces into which conductive paths may be laid out to carry power to the core array or carry dedicated signals to circuits other than the core which also reside on the integrated circuit.

Abstract: A system for hierarchical data storage management and transparent data backup in a high speed, high volume Fibre Channel Arbitrated Loop environment comprising first and second Fibre Channel Arbitrated Loops, each coupling a Transaction Server and backup HSM server to high speed disk drives and mirrored high speed disk drives respectively. The two loops are coupled by a Bridge compatible with the Fibre Channel Arbitrated Loop protocol which forwards write transactions directed to the mirrored disk drives from the first loop the second but keeps read transaction from the Transaction Server to the high speed disk drives on the first loop isolated from backup and HSM transactions occurring on the second loop between the backup HSM server, the mirrored disk drives and backup storage devices coupled to the backup HSM server.

Abstract: A learning half bridge and bridge for a Fibre Channel Arbitrated Loop and switching protocol. A half bridge can be coupled to a local loop segment and a remote loop segment. The half bridge includes transmit and receive ports implementing predetermined switching and conflict resolution rules and a memory storing a forwarding table. Typically the switching rules are implemented using state machines. The state machines implement a switching protocol that controls transitions between states which control switching connections, writing of data to memory and reading of data from memory and preemption of conflicting OPN primitives. Each half bridge includes a local return segment that can be switched by the state machines to bypass the remote loop segment if both the source node and destination node are on the local loop segment so as to make the local loop segment a complete Fibre Channel Arbitrated Loop.

Abstract: A configurable SRAM for a field programmable gate array. Two memory arrays each have a data input, a data output, a write enable input and port A and B address inputs. First and second address buses are selectively coupled to the port A and port B address inputs through multiplexers such that different configurations can be achieved. The multiplexers are controlled by a dual port/single port steering signal and a x1/x2 steering signal such that the following configurations can be achieved: 32 x1 dual port; 32 x1 single port and 16 x2 single port. In dual port configurations, simultaneous read and write operations to different cells can occur. In x2 configuration, each array is operated as an independent memory with its own address input, its own data output and its own data input.