Patents Represented by Attorney, Agent or Law Firm Ronald C. Fish
  • Patent number: 6782474
    Abstract: A network device (100, 300) is connected to a network (102) having also a management station (107) connected thereto. The method for configuring the network device comprises the steps of transmitting from the management station a configuration packet to the network device (201), authenticating at the network device the management station as the genuine transmitter of the configuration packet (202) and decoding the configuration parameters contained in said configuration packet and storing them as the configuration parameters of the network device (203).
    Type: Grant
    Filed: June 4, 1999
    Date of Patent: August 24, 2004
    Assignee: SSH Communication Security Ltd.
    Inventor: Tatu Ylonen
  • Patent number: 6715233
    Abstract: A modular, expandable, self-regulating watering system for burial in planters, which do not have access to water pipes nearby for use in watering plants continuously with on the amount of water the plant needs and which can be refilled by relatively infrequent visits. The system is comprised of a plurality of hollow sections each of which has two upper ports and two lower ports, unless there are only two sections in which case only one upper port and one lower port is needed on each section. One section has a fill pipe that extends above the soil level. One section has an air port at the top thereof, or close to the top, which is coupled to an air tube, which is plugged at the other end with a hydrophilic sensor. Expansion sections can be added or subtracted to make the system larger or smaller. All sections are coupled together at their upper ports by flexible hose or tubing, and are coupled together by their lower ports by flexible hose or tubing.
    Type: Grant
    Filed: January 28, 2002
    Date of Patent: April 6, 2004
    Assignee: Planter Technology, Inc.
    Inventor: Christopher Lyon
  • Patent number: 6459703
    Abstract: A method for allowing upstream channels having the same multiplexing type but different symbol rates or the same symbol rates but different multiplexing types to be transmitted on the same frequency band without interfering with each other. In particular, a method for allowing DOCSIS 1.0 TDMA only cable modems to coexist on a digital data delivery distributed system with advanced PHY TDMA or SCDMA mode cable modems without the need for modification of the DOCSIS 1.0 cable modems or the need for the DOCSIS 1.0 modems to transmit on a different frequency.
    Type: Grant
    Filed: June 21, 1999
    Date of Patent: October 1, 2002
    Assignee: Terayon Communication Systems, Inc.
    Inventors: Michael Grimwood, Paul Alan Lind, Selim Shlomo Rakib
  • Patent number: 6426983
    Abstract: A narrow band interference excision circuit for use in broadband digital data communication systems such as CDMA systems. The excision circuit is comprised of a matrix of polyphase filters that divide the input signal into a plurality of narrow subbands. Each narrow subband signal is examined to determine if narrowband interference exists in that bin. This is done preferably by computing the average power of the subband signal. If a signal in a bin has an average power greater than some adjustable or adaptive threshold, then the entire subband signal is eliminated. A bank of polyphase synthesis filters reassembles the composite signal. An equalization circuit with an error predictor comprised of an adaptive FIR filter is coupled to adapt coefficients of the filter and generate a colored noise cancellation signal to remove colored noise from the input to the slicer.
    Type: Grant
    Filed: September 14, 1998
    Date of Patent: July 30, 2002
    Assignee: Terayon Communication Systems, Inc.
    Inventors: Selim Shlomo Rakib, Yoram Zarai
  • Patent number: 6426947
    Abstract: A system for reducing the cost of network managment by using a proxy agent and subchannel communications so fewer SNMP licenses and fewer protocol stacks are needed. Subchannel communication is achieved in a plurality of different embodiments. Embodiments having single subchannel transceivers, multiple transceivers, single multiplexer and multiple multiplexers are disclosed. An NMS process using routing table CRC to automatically detect when the NMS topology information is incorrect and automated topology discovery is disclosed. A process for automated discovery of redundant cables during automated topology discovery is disclosed.
    Type: Grant
    Filed: October 21, 1998
    Date of Patent: July 30, 2002
    Inventors: Kim K. Banker, Christopher Alan Del Signore, Gavin Bowlby
  • Patent number: 6307868
    Abstract: A system for bidirectional communication of digital data between a central unit and a remote unit wherein the need for tracking loops in the central unit has been eliminated. The central unit transmitter generates a master carrier and a master clock signal which are used to transmit downstream data to the remote units. The remote units recover the master carrier and master clock and synchronize local oscillators in each remote unit to these master carrier and master clock signals to generate reference carrier and clock signals for use by the remote unit receiver. These reference carrier and clock signals are also used by the remote unit transmitters to transmit upstream data to the central unit. The central unit receiver detects the phase difference between the reference carrier and clock signals from the remote units periodically and adjusts the phase of the master carrier and master clock signals for use by the central unit receiver to receive the upstream data.
    Type: Grant
    Filed: July 16, 1997
    Date of Patent: October 23, 2001
    Assignee: Terayon Communication Systems, Inc.
    Inventors: Selim Shlomo Rakib, Yehuda Azenkot
  • Patent number: 6295272
    Abstract: A method and apparatus for implementing a subchannel for management and control or other supplemental data on a media shared with a high speed data link. Several FDMA approaches are disclosed including AM, FM, PM, phase, QAM, QPSK etc. modulation of a subcarrier having a frequency which is in the bandwidth provided by the shared media which is not used by the DC balanced high speed data stream. A preferred species which is compatible with existing high speed data transmitters and receivers comprises a subchannel transmitter which frequency shift keys a subchannel carrier of about 1 mHz with the subchannel data. The modulated subchannel carrier is summed by superposition with a DC balanced NRZ format gigabit data stream and coupled onto the media.
    Type: Grant
    Filed: April 20, 1998
    Date of Patent: September 25, 2001
    Assignee: Gadzoox Networks, Inc.
    Inventors: Richard Feldman, Alistair Black
  • Patent number: 6253321
    Abstract: A data processing system implements a security protocol based on processing data in packets. The data processing system comprises processing packets for storing filter code and processing data packets according to stored filter code, and a policy managing function for generating filter code and communicating generated filter code for packet processing. The packet processing function is arranged to examine, whether the stored filter code is applicable for processing a certain packet. If the stored filter code is not applicable for the processing of a packet, the packet is communicated to the policy managing function, which generates filter code applicable for the processing of the packet and communicates the generated filter code for packet processing.
    Type: Grant
    Filed: June 19, 1998
    Date of Patent: June 26, 2001
    Assignee: SSH Communications Security Ltd.
    Inventors: Pekka Nikander, Tatu Ylonen
  • Patent number: 6243386
    Abstract: A learning half bridge and bridge for a Fibre Channel Arbitrated Loop and switching protocol. A half bridge can be coupled to a local loop segment and a remote loop segment. The half bridge includes transmit and receive ports implementing predetermined switching and conflict resolution rules and a memory storing a forwarding table. Typically the switching rules are implemented using state machines. The state machines implement a switching protocol that controls transitions between states which control switching connections, writing of data to memory and reading of data from memory and preemption of conflicting OPN primitives. Each half bridge includes a local return segment that can be switched by the state machines to bypass the remote loop segment if both the source node and destination node are on the local loop segment so as to make the local loop segment a complete Fibre Channel Arbitrated Loop.
    Type: Grant
    Filed: September 14, 1999
    Date of Patent: June 5, 2001
    Assignee: Gadzoox Networks, Inc.
    Inventors: Kurt Chan, Alistair D. Black
  • Patent number: 6243369
    Abstract: A bidirectional digital data communication system which generate phase coherent upstream clock and carrier signals from recovered downstream clock generated from a master clock in a central unit. The preferred species uses any downstream clock rate and generates a phase coherent upstream clock so long as the two clock rates can be related by the ratio M/N where M and N are integers. One embodiment uses an MCNS downstream and an SCDMA upstream and uses MNCN timestamp messages in the downstream to achieve an estimate of RU frame offset prior to establishing frame alignment using a ranging process. The use of timestamp messages to estimate the offset is aided by a low jitter method for inserting timestamp messages by avoiding straddling of MPEG packet headers with the sync message. Clock slip is detected by counting upstream clock cycles over a predetermined downstream clock interval and the RU transmitter is shut down if slip is detected to prevent ISI interference from misaligned codes.
    Type: Grant
    Filed: May 6, 1998
    Date of Patent: June 5, 2001
    Assignee: Terayon Communication Systems, Inc.
    Inventors: Michael Grimwood, Jim Knittel, Paul Richardson, Selim Shlomo Rakib, Paul Alan Lind, Doug Artman
  • Patent number: 6232913
    Abstract: Characteristics of a target are measured by a radar or sonar. Pulses (101, 102, 103) are transmitted and in between (X) the transmissions of pulses a signal is received which depends on the transmitted pulses and on the distribution of the characteristics measured at different ranges. The distribution at different ranges of the characteristics measured is determined by representing it by means of a substantially linear system of equations in which the variables are the values of the characteristics measured at desired ranges, and by solving the system of equations for the variables. The transmitted pulses form a cyclically repeated pulse code or a continuously changing pulse train.
    Type: Grant
    Filed: March 24, 1999
    Date of Patent: May 15, 2001
    Inventor: Markku Sakari Lehtinen
  • Patent number: 6222757
    Abstract: A configuration memory architecture for an FPGA that eliminates the need for a regular array of word lines and bit lines is disclosed. The memory is comprised, in the preferred embodiment, of a plurality of memory bytes. Each memory byte has eight SRAM latches, a single flip flop and a one-of-eight decoder having a data input coupled to the inverting output of the flip flop and eight individual data outputs, each of which is coupled to a data input of one of the SRAM latches. The decoder also has address and write control inputs which are coupled to a state machine or other programmable device that controls the sequencing of the loading operation to load configuration data into the memory. The flip flops of all the memory bytes are coupled together in a serpentine shift register.
    Type: Grant
    Filed: February 25, 1998
    Date of Patent: April 24, 2001
    Assignee: Xilinx, Inc.
    Inventors: Prasad Rau, Atul V. Ghia, Suresh M. Menon
  • Patent number: 6218858
    Abstract: A programmable input/output structure comprised of three input circuits and one output circuit coupled to the pin of an FPGA with the input circuits and output circuits being selectively enabled by programming bits so that input signals may be accepted from TTL, GTL, GTLP, LVPECL or LVDS type external circuits. The programming bits can also selectively enable an output driver to simultaneously drive the same pin of the FPGA as an output with signals which are either TTL or GTL or GTLP compatible. Further, the slew rate of the output driver is programmable between slow, medium or fast.
    Type: Grant
    Filed: January 27, 1999
    Date of Patent: April 17, 2001
    Assignee: Xilinx, Inc.
    Inventors: Suresh Manohar Menon, Yogendra Kumar Bobra, Atul V. Ghia, Arch Zaliznyak
  • Patent number: 6212503
    Abstract: When data is simply input without being aware of describing a program language (e.g., COBOL or FORTRAN), the data input meaning is detected, and software for this data processing is automatically applied and prepared. Various types of worksheets corresponding to the business logic terms and data input positions are stored in a business data file. When an operation unit is operated and data is input to the data input position, the input data is stored as rule setting data. When application data corresponding to the rule setting data is input through the operation unit, a business logic applying section determines the use software in accordance with the corresponding business logic term.
    Type: Grant
    Filed: July 22, 1998
    Date of Patent: April 3, 2001
    Assignee: Knowledge Modeling Institute Inc.
    Inventor: Tadao Matsuzuki
  • Patent number: 6198427
    Abstract: A series of police doppler single mode radars and a multimode police doppler radar, all with direction sensing capability are disclosed. A quadrature front end which mixes received RF with a local oscillator to generate two channels of doppler signals, one channel being shifted by an integer multiple of 90 degrees in phase relative to the other by shifting either the RF or the local oscillator signal being fed to one mixer but not the other. The two doppler signals are digitized and the samples are processed by a digital signal processor programmed to find one or more selected target speeds. Single modes disclosed are: stationary strongest target; stationary, fastest target; stationary, strongest and fastest targets; moving, strongest, opposite lane; moving, strongest, same lane; moving, fastest, opposite lane; moving, fastest and strongest, opposite lane; moving, fastest, same lane; moving fastest and strongest, same lane.
    Type: Grant
    Filed: July 21, 1998
    Date of Patent: March 6, 2001
    Assignee: Applied Concepts, Inc.
    Inventors: John L. Aker, Robert S. Gammenthaler
  • Patent number: 6192054
    Abstract: An apparatus for accelerated Fiber Channel protocol handshaking and data exchange involves dividing a Fiber Channel arbitrated loop architecture up into a plurality of arbitrated subloops, each of which arbitrates locally using the same fundamentals as the Fiber Channel arbitration protocol but with some slight modifications which do not affect the compatibility of standard Fiber Channel nodes. Each subloop is coupled to a hub port which contains a state machine which implements distributed intelligence to do switching function and fill word generation to implement the accelerated protocol by using a plurality of switching, fill word generation and token passing rules. The state machine in each hub port is coupled to its local subloop and to its neighboring hub ports through a single TDMA bus which has timeslots dedicated to carrying broadcast loop and return loop traffic and control token traffic.
    Type: Grant
    Filed: May 8, 1998
    Date of Patent: February 20, 2001
    Assignee: Gadzoox Networks, Inc.
    Inventors: Kurt Chan, Alistair D. Black
  • Patent number: 5563603
    Abstract: A police radar utilizing digital data transmission from the antenna unit to a separately housed counting and display unit. The antenna has a double balanced mixer to suppress even order harmonics. The counting and display unit has a computer programmed to perform digital signal processing on the digital data received from the antenna to improve the quality and accuracy of calculated speeds for patrol speed, strongest target speed and fastest target speed. Fastest target speed can be displayed simultaneously with strongest target speed. Signal processing techniques are used to suppress false signals caused by double and triple bounce, harmonics, intermodulation products, video display terminal interference, etc.
    Type: Grant
    Filed: February 10, 1995
    Date of Patent: October 8, 1996
    Inventors: John L. Aker, Robert S. Gammenthaler, Alan B. Mead
  • Patent number: 5553732
    Abstract: The object of this invention is to provide a receptacle with a closure cap which is molded simultaneously with the receptacle body by using blow mold machine. A synthetic resin material is introduced into a pair of mold halves and a fluid such as air is injected into the tube to expand the tube against the walls of the mold thereby shaping the receptacle body. The synthetic resin receptacle of this invention comprises a tubular receptacle body 1, a small tube 2 at one end of the tubular receptacle body for filling, a closure cap fitting portion 3 formed at the top end of the vessel body, a diametrically small cut-out portion 5 joining the top end of said closure cap fitting portion and having a small bore, a cap body 4 having reversed-C like shape in a hollow configuration and joining the cutout portion 5. A projection 7 provided in the center portion of the vertical inner surface of said closure cap body plugs the small bore.
    Type: Grant
    Filed: January 13, 1995
    Date of Patent: September 10, 1996
    Assignee: Nikko Seika Kabushiki Kaisha
    Inventor: Koji Kani
  • Patent number: D442390
    Type: Grant
    Filed: November 16, 1999
    Date of Patent: May 22, 2001
    Inventor: Peter Gregory Edwards
  • Patent number: D374615
    Type: Grant
    Filed: December 21, 1994
    Date of Patent: October 15, 1996
    Assignee: Nikko Seika Kabushiki Kaisha
    Inventor: Koji Kani