Abstract: In a microprogrammed data processing system in which the boundaries of the operands or data strings identified by the descriptors are not constrained to coincide with boundaries of the units of addressable memory space, i.e., words, the time required to retrieve, execute and store operands of a three descriptor instruction, wherein two descriptors define the memory address of the initial operands and the third descriptor defines the memory address of the resulting operand, can be reduced by prefetching the two words which include the boundaries of the operand (data string) identified by the third descriptor. After execution of the instruction, the boundary words of the resulting operand (data string) can have the rewrite data, that is the data of the boundary words which are not part of the resulting operand, and should therefore be retained and inserted in appropriate positions of the appropriate boundary word by a retrieval of the boundary words which do not interrupt the normal data processing sequence.

Abstract: There is disclosed herein an apparatus for computerized real time verification of the correctness of pin locations for wire wrap connections made by human operators in constructing or upgrading computer backplanes. A suitably programmed microprocessor operates from a data base consisting of the information from a wire list drawing fed into the microprocessor's memory from a cassette tape record. The microprocessor is linked to the backplane to be verified and to the hand operated wire wrap gun serving as the test probe by a uniquely designed Wire Check System Interface. Both wire adds and wire deletes may be made.

Abstract: In a microprogrammed data processing system, the throughput of the system is increased during the processing of decimal numeric instructions by apparatus which, in response to a microword indicating that the result of the decimal numeric calculation is a short operand, that is, a predetermined number of words or less, and in accordance with an instruction descriptor, generates a count of the number of words of the resultant operand the decimal unit will transfer to memory.

Abstract: An improved method of forming raised input/output (I/O) terminals on the top surfaces of semiconductor elements of a semiconductor wafer. After via openings are formed through the passivation layer of such elements at locations where the I/O terminals are to be formed, which openings provide access to the metalization layers of the elements photolithographic techniques using a layer of heat resistant photoresist which is laminated to the top surface of the wafer are used to form openings through the photoresist layer to provide access to the metalization layers through the vias. A barrier metal layer is deposited on the exposed surfaces of the photoresist, and the metalization layers, and passivation layer of the elements. The barrier metal layer overlying the photoresist and then the photoresist are stripped from the wafer. The same photolithographic techniques using the same heat resistant photoresist material are used to define openings surrounding the barrier metal lining the via openings.

Abstract: Apparatus for resolving the priority of a plurality of input/output devices. The device request signals and signals indicating the channel number of the currently active channel program are applied to the address terminals of a programmable read only memory. Each address location stores bits indicative of the next priority device for the given input conditions.

Abstract: There is disclosed herein an apparatus for verifying the correct placement of a wire wrap tool on a wire wrap pin in an array of pins. An outside source of pin and condition data such as a human operator operating switches or a mechanical sequential state machine or a hand wired logic sequential state machine supplies binary data indicating the correct pin and the expected electrical condition to be found on the correct pin. A wire check system interface means in combination with a wire wrap tool, a strip switch and a number of HDMUG logic boards then subject the correct pin to the expected electrical condition and compare the electrical condition on the pin actually touching the wire wrap tool to the expected electrical condition and signals the correctness or incorrectness of placement of the wire wrap tool.

Abstract: In a microprogrammed data processing system, the throughput of the system is increased during the processing of decimal numeric instructions by apparatus which is conditioned by the instruction descriptors in advance of receiving the operands to align the decimal digits of the operand words as the words are received by the apparatus from memory.The descriptor information for each operand includes the scale factor, the position of the sign, the position of the most significant character within the word, whether it is a floating point or scaled operand, the number of bits in each decimal character, either 4 or 9 bits, and the length of the operand.The apparatus is conditioned by the descriptor information to align the two operands for processing.

Abstract: A cache unit includes a cache store organized into a number of levels to provide a fast access to instructions and data words. Directory circuits, associated with the cache store, contain address information identifying those instructions and data words stored in the cache store. The cache unit has at least one instruction register for storing address and level signals for specifying the location of the next instruction to be fetched and transferred to the processing unit. Replacement circuits are included which, during normal operation, assign cache locations sequentially for replacing old information with new information. The cache unit further includes apparatus operative in response to a first predetermined type of command specifying the fetching of data words to set an indicator flag to a predetermined state.

Abstract: A memory subsystem includes a memory board comprising of a number of memory chips positioned at a corresponding number of physical row locations. The memory chips are one of two types selected to provide a predetermined memory capacity. The board further includes a number of decoder circuits connected to generate a corresponding number of sets of chip select signals in response to address signals applied thereto. These signals are applied through corresponding sets of logic circuits for application to the memory chips of each row. Additionally, logic gating circuits logically combine predetermined chip select signals for generating additional chip select signals. These additional chip select signals are applied through switches, the outputs of which are applied to predetermined ones of the sets of logic circuits. When the switches are positioned in a predetermined manner, the additional chip select signals are directed to only predetermined one of the physical row locations via the sets of logic circuits.

Abstract: Apparatus in a Cathode Ray Tube (CRT) display allows the sharing of the system bus between the microprocessor (CPU) and Direct Memory Access (DMA) devices without degrading the CPU performance by splitting the system bus cycle into an address phase and a data phase.

Abstract: An impact matrix printing head for use in a computer printer. The printing head utilizes a unique design to provide an unitary needle guiding assembly and an unitary electromagnet assembly which can each be independently removed from the printer head without the need to disassemble. The printer head includes adjustments for the air gap of the electromagnet assembly and adjustments for the needle position, both initially and after needle wear has occurred.

Abstract: A hardware/firmware communication line adapter for interfacing a communication processor to a broadband high level data link communication channel. Transmit and receive data and control characters received either from the processor or from a communication channel device are processed under the control of the adapter firmware to effectuate CRC checking, byte size control, extended and variable field format control, partial last byte control, and block transfer control functions on the transmitted/received data stream. First-in-first-out (FIFO) buffer memories are employed in the transmit circuits to queue a frame of transmit data and control characters at the adapter whereby the communication processor/adapter interface control is simplified. Similarly, a FIFO buffer is employed in the receive circuits to reduce the frequency of receive interrupts and to enable block transfer of received data to the processor.

Abstract: A remote maintenance apparatus for performing maintenance via a communication channel. Hardware is provided to retain information in a special channel which can be accessed by a remote communication system, in the event of malfunction in the computer system. An additional feature of this hardware is increased speed and efficiency in addressing when the computer system is operating normally.

Abstract: A printed circuit board assembly includes at least two layers which is able to accommodate a subsystem such as a memory subsystem designed to have one or more optional features. The two layers of the printed circuit board when etched include the required number of horizontal and vertical paths to be connected to all of the integrated circuit chips to be positioned and interconnected thereon. The required holes for such integrated circuit chips when drilled include first sets of holes for mounting groups of integrated circuit chips required for implementing a first group of features and which are to be interconnected to the other integrated circuit chips of the subsystem mounted on the different sections of the board. Second sets of holes are included on the board so as to have a predetermined relationship with the first sets of holes for mounting alternative groups of integrated circuit chips to be interconnected in a manner to implement other features.

Abstract: A multi-way vectored interrupt automatically addresses any one of a plurality of locations in a memory according to a unique function code. Hardware is provided which disables the normal paging addressing apparatus of a processor and enables an indirect addressing mechanism when a predetermined location in memory is addressed.

Abstract: A hardware/firmware control system is disclosed for accommodating the concurrent bi-directional transfer of information between a communications channel such as a telephone line and a communications processor in a data processing system.

Abstract: Computer apparatus in a word organized computer system for implementing a single computer instruction for moving a binary number stored in one of a plurality of addressable registers to a designated memory location in a word addressable memory. The binary number is divisible into a maximum of four characters with characters of a given number having either 8 or 9 bits, and a word has 36 bits divisible into four bytes. If the characters have 8 bits, the characters are reformatted so that there is one character per byte. If the characters have 9 bits, they are not reformatted since there is already only one character per byte. The bytes are then shifted so that the byte position containing the most significant character of the binary number occupies a designated byte position in a first word stored in a data out register ready to be read into memory for storage at the designated memory location.

Abstract: A logic control system for a video display terminal is disclosed for accommodating vertically and horizontally varying entry points to a video memory to acquire first character bytes of rows of video information for display on a CRT screen. Dynamically changeable display page snapshots of the video memory, and the formation of display pages from randomly located rows of video information within the video memory are thereby provided.

Abstract: A data communication simulator system wherein the basic operational conditions of a bit and byte synchronized data network may be simulated by generation of a bit timing signal, a byte timing signal, data signals, and control and status indication signals. Manual as well as automatic testing modes are provided, the manual mode including a signal stepping control arranged to enable either full or half cycle operation.

Abstract: A reusable fixture for a segment of a film strip having a flexible beam lead frame mounted on the segment and an integrated circuit chip bonded to the inner portions of the leads of the lead frame. The fixture is made from an integral laminar layer of a suitable material. The improvements are in providing a plurality of pairs of projections with protuberances which overlie, to a slight degree, the attachment webs of a segment. The fixture is also provided with detachment openings to provide access to the attachment webs which detachment openings facilitate removal of a segment from the fixture.