Patents Represented by Attorney Rosemary L. S. Pike
  • Patent number: 6753260
    Abstract: A new method of forming a composite etching stop layer is described. An etching stop layer is deposited on a substrate wherein the etching stop layer is selected from the group consisting of: silicon carbide, silicon nitride, SiCN, SiOC, and SiOCN. A TEOS oxide layer is deposited by plasma-enhanced chemical vapor deposition overlying the etching stop layer. The composite etching stop layer has improved moisture resistance, better etching selectivity, and lower dielectric constant than other etching stop layers.
    Type: Grant
    Filed: October 5, 2001
    Date of Patent: June 22, 2004
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Lain-Jong Li, Tien-I Bao, Shwang-Ming Jeng, Syun-Ming Jang, Jun-Lung Huang, Jeng-Cheng Liu
  • Patent number: 6750519
    Abstract: Methods for forming dual-metal gate CMOS transistors are described. An NMOS and a PMOS active area of a semiconductor substrate are separated by isolation regions. A metal layer is deposited over a gate dielectric layer in each active area. Silicon ions are implanted into the metal layer in one active area to form an implanted metal layer which is silicided to form a metal silicide layer. Thereafter, the metal layer and the metal silicide layer are patterned to form a metal gate in one active area and a metal silicide gate in the other active area wherein the active area having the gate with the higher work function is the PMOS active area. Alternatively, both gates may be metal silicide gates wherein the silicon concentrations of the two gates differ. Alternatively, a dummy gate may be formed in each of the active areas and covered with a dielectric layer. The dielectric layer is planarized thereby exposing the dummy gates. The dummy gates are removed leaving gate openings to the semiconductor substrate.
    Type: Grant
    Filed: October 8, 2002
    Date of Patent: June 15, 2004
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Wenhe Lin, Mei-Sheng Zhou, Kin Leong Pey, Simon Chooi
  • Patent number: 6746914
    Abstract: A first and second damascene copper interconnect plug are created over the surface of a substrate. A MIM capacitor, which is aligned with the second damascene copper interconnect plug, is created by a one-time etch of a stack of layers comprising Ta/capacitor dielectric/Ta. Copper interconnects are then created aligned with the MIM capacitor and the second damascene interconnect plug.
    Type: Grant
    Filed: May 7, 2002
    Date of Patent: June 8, 2004
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Shao Kai, Ng Hwei, Sanford Chu
  • Patent number: 6747314
    Abstract: A method to form a closely-spaced, vertical NMOS and PMOS transistor pair in an integrated circuit device is achieved. A substrate comprise silicon implanted oxide (SIMOX) wherein an oxide layer is sandwiched between underlying and overlying silicon layers. Ions are selectively implanted into a first part of the overlying silicon layer to form a drain, channel region, and source for an NMOS transistor. The drain is formed directly overlying the oxide layer, the channel region is formed overlying the drain, and the source is formed overlying the channel region. Ions are selectively implanted into a second part of the overlying silicon layer to form a drain, channel region, and source for a PMOS transistor. The drain is formed directly overlying the oxide layer, the PMOS channel region is formed overlying the drain, and the source is formed overlying the channel region. The PMOS transistor drain is in contact with said NMOS transistor drain.
    Type: Grant
    Filed: September 12, 2002
    Date of Patent: June 8, 2004
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Ravi Sundaresan, Yang Pan, James Yong Meng Lee, Ying Keung Leung, Yelehanka Ramachandramurthy, Jia Zhen Zheng, Lap Chan, Elgin Quek
  • Patent number: 6743694
    Abstract: A new method of forming a laser mark without damage to the wafer surface is described. A pad oxide layer is formed on a silicon wafer. A nitride layer is deposited overlying the pad oxide layer. A first trench is laser cut through the nitride layer and the pad oxide layer into the silicon wafer. The trench is etched to a second depth wherein the nitride layer is used as a hard mask and wherein the trench forms an identification mark.
    Type: Grant
    Filed: April 30, 2002
    Date of Patent: June 1, 2004
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Ching Thiam Chung, Kay Jin Lee
  • Patent number: 6743291
    Abstract: A process of fabricating a CMOS device comprised with super-steep retrograde (SSR), twin well regions, has been developed. The process features the use of two, selective epitaxial growth (SEG), procedures, with the first SEG procedure resulting in the growth of bottom silicon shapes in the PMOS, as well as in the NMOS region of the CMOS device. After implantation of the ions needed for the twin well regions, into the bottom silicon shapes, a second SEG procedure is employed resulting in growth of top silicon shapes on the underlying, implanted bottom silicon shapes. An anneal procedure then distributes the implanted ions resulting in an SSR N well region in the composite silicon shape located in the PMOS region, and resulting in an SSR P well region in the composite silicon shape located in the NMOS region of the CMOS device.
    Type: Grant
    Filed: July 9, 2002
    Date of Patent: June 1, 2004
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Chew Hoe Ang, Wenhe Lin, Jia Zhen Zheng
  • Patent number: 6740592
    Abstract: A method for avoiding current leakage at the shallow trench isolation edge in a border-less contact process is described. Trenches are etched into a semiconductor substrate. An etch stop liner layer is deposited within the trenches and etched back to leave the etch stop liner layer only on sidewalls of the trenches. The trenches are filled with an isolation layer overlying the liner sidewalls and polished back to leave the isolation layer only within the trenches. Semiconductor device structures, including source and drain junctions, are formed in the active areas. An interlevel dielectric layer is deposited over the device structures. Border-less contact openings are etched through the ILD wherein the liner sidewalls act as an etch stop thereby preventing leakage of the source and drain junctions. The contact openings are filled with a conducting layer wherein the liner sidewalls act as a diffusion barrier to the conducting layer.
    Type: Grant
    Filed: December 3, 2001
    Date of Patent: May 25, 2004
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventor: Kelvin Yih Yuh Doong
  • Patent number: 6740580
    Abstract: A method to form copper interconnects is described. The method may be used to form single or dual damascene interconnects. The addition of an aluminum barrier layer to the conventional barrier layer creates a superior barrier to copper diffusion. A substrate layer is provided. A dielectric layer is deposited overlying the substrate layer. The dielectric layer patterned to form interconnect trenches. An optional titanium adhesion layer may be deposited. An aluminum barrier layer is deposited overlying the interior surfaces of the trenches. A second barrier layer, comprising for instance titanium and titanium nitride, is deposited overlying the aluminum barrier layer. A copper layer is deposited overlying the second barrier layer and filling the interconnect trenches. The copper layer, the second barrier layer, and the aluminum barrier layer are polished down to the top surface of the dielectric layer to define the copper interconnects, and complete the fabrication of the integrated circuit device.
    Type: Grant
    Filed: September 3, 1999
    Date of Patent: May 25, 2004
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Subhash Gupta, Chyi S. Chern, Mei Sheng Zhou
  • Patent number: 6737739
    Abstract: A semiconductor chip device package comprised of a semiconductor substrate having semiconductor devices formed on the semiconductor substrate. At least one dielectric layer is over the semiconductor substrate. At least one layer of interconnects is over the semiconductor devices and within the at least one respective dielectric layer with at least a portion of the interconnects being separated by voids having a vacuum or air therein. A passivation layer is over the uppermost of the at least one layer of interconnects. Wherein the semiconductor chip device is vacuum sealed within a semiconductor chip device package.
    Type: Grant
    Filed: October 30, 2002
    Date of Patent: May 18, 2004
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Shyue-Fong Quek, Ting Cheong Ang, Duay Ing Ong, Sang Yee Loong
  • Patent number: 6734101
    Abstract: A new method of reducing copper hillocks in copper metallization is described. An opening is made through a dielectric layer overlying a substrate on a wafer. A copper layer is formed overlying the dielectric layer and completely filling the opening. The copper layer is polished back to leave the copper layer only within the opening. Copper hillocks are reduced by: coating an oxide layer over the copper layer and the dielectric layer, thereafter heating the wafer using NH3 plasma, and thereafter depositing a capping layer overlying the oxide layer wherein the time lapse between polishing back the copper layer and depositing the capping layer is less than one day (24 hours).
    Type: Grant
    Filed: October 31, 2001
    Date of Patent: May 11, 2004
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Tien-I Bao, Jeng Shwang-Ming, Syun-Ming Jang, Chen-Hua Yu, Kuen-Chyr Lee
  • Patent number: 6734072
    Abstract: A method of forming a conductive gate structure on an underlying gate insulator layer, without the use of a plasma dry etch conductive gate definition procedure, has been developed. After formation of source/drain extension (SDE) and heavily doped source/drain regions, an opening is formed in a planarized dielectric layer exposing the top surface of a semiconductor alloy layer, or exposing the top surface of a semiconductor substrate, while the planarized dielectric layer and adjacent insulator spacers overlay the source/drain regions. A multiple spike, rapid thermal oxidation (RTO) procedure is employed to grow a gate insulator layer on the region of semiconductor alloy, or semiconductor, exposed in the opening, with the low temperature RTO procedure, and the planarized dielectric layer overlying the source/drain regions, suppressing out diffusion of SDE dopants.
    Type: Grant
    Filed: March 5, 2003
    Date of Patent: May 11, 2004
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Yung Fu Chong, Alex See
  • Patent number: 6734082
    Abstract: A process for forming a shallow trench isolation (STI), structure in a semiconductor substrate, featuring a group of insulator liner layers located on the surfaces of the shallow trench shape used to accommodate the STI structure, has been developed. After defining a shallow trench shape featuring rounded corners, a group of thin insulator liner layers, each comprised of either silicon oxide or silicon nitride, is deposited on the exposed surfaces of the shallow trench shape via atomic layer depositing (ALD), procedures. A high density plasma procedure is used for deposition of silicon oxide, filling the shallow trench shape which is lined with the group of thin insulator liner layers. The silicon nitride component of the insulator liner layers, prevents diffusion or segregation of P type dopants from an adjacent P well region to the silicon oxide of the STI structure.
    Type: Grant
    Filed: August 6, 2002
    Date of Patent: May 11, 2004
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Jia Zhen Zheng, Soh Yun Siah, Chew Hoe Ang
  • Patent number: 6730591
    Abstract: A method of forming interconnect structures in a semiconductor device, comprising the following steps. A semiconductor structure is provided. In the first embodiment, at least one metal line is formed over the semiconductor structure. A silicon-rich carbide barrier layer is formed over the metal line and semiconductor structure. Finally, a dielectric layer, that may be fluorinated, is formed over the silicon-rich carbide layer. In the second embodiment, at least one fluorinated dielectric layer, that may be fluorinated, is formed over the semiconductor structure. The dielectric layer is patterned to form an opening therein. A silicon-rich carbide barrier layer is formed within the opening. A metallization layer is deposited over the structure, filling the silicon-rich carbide barrier layer lined opening. Finally, the metallization layer may be planarized to form a planarized metal structure within the silicon-rich carbide barrier layer lined opening.
    Type: Grant
    Filed: July 1, 2002
    Date of Patent: May 4, 2004
    Assignees: Chartered Semiconductor Manufactoring Ltd., Institute of Microelectronics
    Inventors: Licheng Han, Xu Yi, Simon Chooi, Mei Sheng Zhou, Joseph Zhifeng Xie
  • Patent number: 6730571
    Abstract: In accordance with the objectives of the invention a new method is provided for creating air gaps in a layer of IMD. First and second layers of dielectric are successively deposited over a surface; the surface contains metal lines running in an Y-direction. Trenches are etched in the first and second layer of dielectric in an X and Y-direction respectively. The trenches are filled with a layer of nitride and polished. A thin layer of oxide is deposited over the surface of the second layer of dielectric. Openings are created through the thin layer of oxide that align with the points of intersect of the nitride in the trenches in the layers of dielectric. The nitride is removed from the trenches by a wet etch, thereby opening trenches in the layers of dielectric with both sets of trenches being interconnected. The openings in the thin layer of oxide are closed, leaving a network of trenches containing air in the two layers of dielectric.
    Type: Grant
    Filed: October 14, 1999
    Date of Patent: May 4, 2004
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Lap Chan, Cher Liang Cha, Kheng Chok Tee
  • Patent number: 6731534
    Abstract: Described are a method and device for tracking memory cell currents using a tracking memory cell circuit wherein the challenges resulting from current degradation and process variations are eliminated. A special strap cell is provided to eliminate ground bounce phase shifting. The tracking and strap cells along with the tracking scheme allow for better tracking of current within the array without the necessity of adding timing margin. The tracking memory cell circuit is a modified version of the memory cell used in the memory array and provides a reference current for the sense amplifier that is compared against the addressed memory cell. Tracking cells are placed in the center of the memory array making them nearer to the active memory cells. As a result, they better mirror the physical and electrical characteristics of the active memory cells over previous methods.
    Type: Grant
    Filed: January 7, 2003
    Date of Patent: May 4, 2004
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventor: Chang Meng Fan
  • Patent number: 6730573
    Abstract: An improved process for fabricating simultaneously high capacitance, less than 0.13 micron metal-insulator-metal capacitors, metal resistors and metal interconnects, has been developed using single or dual damascene processing. The key advantage is the use of only one additional mask reticle to form both MIM capacitor and resistor, simultaneously. Several current obstacles that exist in BEOL, back end of line, are overcome, namely: (a) the use of two or more photo-masks to make <0.13 um MIM capacitors, (b) undulated copper surfaces, when dielectrics are deposited directly upon it, (c) particles generation concerns during etching, when attempting an etch stop on the bottom MIM plate layers, and finally, (d) dishing during CMP occurs when large copper MIM plates are required, with subsequent capacitance matching problems. The integrated method overcomes the above obstacles and simultaneously forms MIM capacitors, metal resistors and metal interconnects using damascene processing.
    Type: Grant
    Filed: November 1, 2002
    Date of Patent: May 4, 2004
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Chit Hwei Ng, Chaw Sing Ho, Lup San Leong, Shao Kai, Raymond Jacob Joy, Sanford Chu, Sajan Marokkey Raphael
  • Patent number: 6727183
    Abstract: A novel etching method for preventing spiking and undercutting of an ultra low-k material layer in damascene metallization is described. A region to be contacted is provided in or on a semiconductor substrate. A liner layer is deposited overlying the region to be contacted. An ultra low-k dielectric layer is deposited overlying the liner layer. A damascene opening is etched through the ultra low-k dielectric layer to the liner layer overlying the region to be contacted wherein this etching comprises a high F/C ratio etch chemistry, high power, and low pressure. The liner layer within the damascene opening is etched away to expose the region to be contacted wherein this etching comprises a high F/C ratio etch chemistry, low power, and low pressure to complete formation of a damascene opening in the fabrication of an integrated circuit device.
    Type: Grant
    Filed: July 27, 2001
    Date of Patent: April 27, 2004
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Ching-Hui Ma, Jen-Cheng Liu, Li-Chih Chao
  • Patent number: 6728585
    Abstract: Described is a personal on-demand audio entertainment system with a base unit attached to a personal computer or other source, a headphone unit and a remote control unit. The base unit transmits digital audio content to the headphone unit using infrared, radio frequency, magnetic or electromagnetic coupling. These data are stored in solid-state memory within the headphone unit. In the headphone unit, the stored digital audio content is converted to analog audio signals, amplified and sent to transducers for conversion to audio signal for the listener during playback. The system is designed such that playback may occur during the downloading process. The remote control unit also uses infrared, radio frequency, magnetic or electromagnetic coupling for communication to the headphone unit. This communication is made using a different channel and does not interfere with the audio data downloading.
    Type: Grant
    Filed: October 3, 2001
    Date of Patent: April 27, 2004
    Assignee: FreeSystems Pte, Ltd.
    Inventor: Chong Lim Neoh
  • Patent number: 6726545
    Abstract: A linear polishing apparatus for polishing a semiconductor substrate including a novel polishing belt arrangement with at least two polishing belts forming a continuous loop. Each belt having an outside polishing surface and an inside smooth surface. The belts are spaced alongside each other sharing a common axis at each end. The belts are looped around a pair of rollers making up a driver roller at one end and a driven roller at the other end. A platen member interposes each belt and is placed between the pairs of rollers. The platen provides a polishing plane and supporting surface for the polishing belts. The polishing plane includes a plurality of holes communicating with an elongated plenum chamber underlying the plane. The chamber supplies a compressed gas to impart an upward pressure against the polishing belts. The driver rollers are coupled to separate motors to independently drive and control at least said two of the polishing belts.
    Type: Grant
    Filed: April 26, 2002
    Date of Patent: April 27, 2004
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Subramanian Balakumar, Chen Feng, Victor Lim, Paul Proctor, Mukhopadhyay Madhusudan, Chivukula Subrahmanyam, Yelehanka Ramachandramurthy Pradeep
  • Patent number: 6727151
    Abstract: A method for forming a MOSFET having an elevated source/drain structure is described. A sacrificial oxide layer is provided on a substrate. A polish stop layer is deposited overlying the sacrificial oxide layer. An oxide layer is deposited overlying the polish stop layer. An opening is formed through the oxide layer and the polish stop layer to the sacrificial oxide layer. First polysilicon spacers are formed on sidewalls of the opening wherein the first polysilicon spacers form an elevated source/drain structure. Second polysilicon spacers are formed on the first polysilicon spacers. The oxide layer and sacrificial oxide layer exposed within the opening are removed. An epitaxial silicon layer is grown within the opening. A gate dielectric layer is formed within the opening overlying the second polysilicon spacers and the epitaxial silicon layer. A gate material layer is deposited within the opening.
    Type: Grant
    Filed: August 7, 2002
    Date of Patent: April 27, 2004
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Yung Fu Chong, Randall Cher Liang Cha, Alex See