Abstract: A STT-MRAM integration scheme is disclosed wherein the connection between a MTJ and CMOS metal is simplified by forming an intermediate via contact (VAC) on a CMOS landing pad, a metal (VAM) pad that contacts and covers the VAC, and a MTJ on the VAM. A dual damascene process is performed to connect BIT line metal to CMOS landing pads through VAC/VAM/MTJ stacks in a device region, and to connect BIT line connection pads to CMOS connection pads through BIT connection vias outside the device region. The VAM pad is a single layer or composite made of Ta, TaN, or other conductors which serves as a diffusion barrier, has a highly smooth surface for MTJ formation, and provides excellent selectivity with refill dielectric materials during a chemical mechanical polish process. Each VAC is from 500 to 3000 Angstroms thick to minimize additional circuit resistance and minimize etch burden.

Abstract: Systems and methods for camera modules having a movable lens barrel, allowing a maximum lens diameter with minimal outside dimensions are disclosed. At least one single linear actuator is moving the lens barrel. Each actuator is deployed in an own corner of the camera module. The moving lens barrel is guided by rolling elements bearings. The actuator comprises a stator, comprising one or more coils wrapped around a rod of magnetic metal and an anchor comprising one or more permanent magnets, which are tightly attached to the lens barrel. An offset between the longitudinal center line of magnets of the anchor and the center of the stator generates a permanent force pushing the lens barrel in direction of the stator of the motor and consequently pushes protrusions on the lens barrel onto the rolling elements bearings, thus preventing the bearings to fall apart in case of a mechanical shock.

Abstract: A non-volatile DRAM cell includes a pass-gate transistor and a cell capacitor. A read operation of the non-volatile cell begins by negatively charging the cell capacitor. A cell capacitor of an associated dummy non-volatile DRAM cell is fully discharged. The pass-gate transistor is activated and if the pass-gate transistor is programmed it does not turn on and if it is erased, it turns on. Charge is shared on the complementary pair of precharged bit lines connected to the non-volatile DRAM cell and its associated Dummy non-volatile DRAM cell. A sense amplifier detects the difference in the data state stored in the pass-gate transistor. The program and erase of the non-volatile DRAM cell is accomplished by charge injection from the associated bit line of the non-volatile DRAM cell.

Abstract: A summing-tracking quantizer additively combines multiple feed-forward outputs of cascaded integrator stages of a sigma-delta analog-to-digital converter with a scaled sampled analog signal, and a delayed scaled analog input signal. The summing tracking quantizer compensates for loop delay within a sigma-delta analog-to-digital converter. A loop delay compensation digital-to-analog converter for a sigma-delta analog-to-digital converter is merged with the voltage reference generator within the summing-tracking quantizer. The summing tracking quantizer selects reference voltages from the voltage reference generator based on a previous digital output code. The summing-tracking quantizer has a matrix switch that receives the previous digital output code and selects the reference voltage for applying to comparators for determining a differential quantization code that is additively combined to the previous digital output code to determine the present digital output code.

Abstract: A microwave assisted magnetic recording writer is disclosed with an octagonal write pole having a top portion including a trailing edge that is self aligned to a spin transfer oscillator (STO). Leading and trailing edges are connected by two sidewalls each having three sections. A first section on each side is coplanar with the STO sidewalls and is connected to a sloped second section at a first corner. Each second section is connected to a third section at a second corner where the distance between second corners is greater than the distance between first corners. A method of forming the writer begins with a trapezoidal shaped write pole in an insulation layer. Two ion beam etch (IBE) steps are used to shape top and middle portions of the write pole and narrow the pole width to <50 nm without breakage. Finally, a trailing shield is formed on the STO.

Abstract: A spin transfer oscillator with a seed/SIL/spacer/FGL/capping configuration is disclosed with a composite seed layer made of Ta and a metal layer having a fcc(111) or hcp(001) texture to enhance perpendicular magnetic anisotropy (PMA) in an overlying (A1/A2)X laminated spin injection layer (SIL). Field generation layer (FGL) is made of a high Bs material such FeCo. Alternatively, the STO has a seed/FGL/spacer/SIL/capping configuration. The SIL may include a FeCo layer that is exchanged coupled with the (A1/A2)X laminate (x is 5 to 50) to improve robustness. The FGL may include an (A1/A2)Y laminate (y=5 to 30) exchange coupled with the high Bs layer to enable easier oscillations. A1 may be one of Co, CoFe, or CoFeR where R is a metal, and A2 is one of Ni, NiCo, or NiFe. The STO may be formed between a main pole and trailing shield in a write head.

Abstract: A TAMR head is disclosed with a triangular shaped plasmon antenna covered on two sides with a plasmon layer that generates an edge plasmon mode along a vertex of the two plasmon sides formed opposite a main pole layer. A plasmon shield (PS) is formed along the ABS and opposite the vertex to confine an electric field from the edge plasmon mode within a small radius of the edge plasmon tip thereby reducing the optical spot size on the magnetic medium and enhancing writability. An end of a waveguide used to direct input electromagnetic radiation to the plasmon antenna adjoins a PS side opposite the ABS. In one embodiment, a magnetic shield may be formed along the ABS and adjoins the PS so that a first PS section terminates at the ABS and faces the vertex while a second PS section is formed between the magnetic shield and waveguide end.

Abstract: A nonvolatile memory device includes an array of EEPROM configured nonvolatile memory cells each having a floating gate memory transistor for storing a digital datum and a floating gate select transistor for activating the floating gate memory transistor for reading, programming, and erasing. The nonvolatile memory device has a row decoder to transfer the operational biasing voltage levels to word lines connected to the floating gate memory transistors for reading, programming, verifying, and erasing the selected nonvolatile memory cells. The nonvolatile memory device has a select gate decoder circuit transfers select gate control biasing voltages to the select gate control lines connected to the control gate of the floating gate select transistor for reading, programming, verifying, and erasing the floating gate memory transistor of the selected nonvolatile memory cells.

Abstract: An apparatus and method for operating an array of NOR connected flash nonvolatile memory cells erases the array in increments of a page, block, sector, or the entire array while minimizing sub-threshold leakage current through unselected nonvolatile memory cells. The apparatus has a row decoder circuit and a source decoder circuit for selecting the nonvolatile memory cells for providing biasing conditions for reading, programming, verifying, and erasing the selected nonvolatile memory cells while minimizing sub-threshold leakage current through unselected nonvolatile memory cells.

Abstract: A CPP-GMR spin valve having a CoFe/NiFe composite free layer is disclosed in which Fe content of the CoFe layer ranges from 20 to 70 atomic % and Ni content in the NiFe layer varies from 85 to 100 atomic % to maintain low Hc and ?S values. A higher than normal Fe content in the CoFe layer improves the MR ratio by ?16% compared with conventional CoFe/NiFe free layers in which the Fe content in CoFe is typically <20 atomic % and the Ni content in NiFe is <85 atomic %. The CPP-GMR performance may also be optimized by incorporating a confining current path layer in the copper spacer between the pinned layer and free layer. For a pinned layer with an AP2/Ru/AP1 configuration, the spin valve performance is further improved by an AP1 layer comprised of a lamination of CoFe and Cu layers as in [CoFe/Cu]2/CoFe.

Abstract: A high performance TMR sensor with a spacer including at least one metal layer such as Cu and one or more MgO layers is disclosed. In addition, there may be a metal dopant in the MgO layer. In an alternative embodiment, the MgO layer may be replaced by other low band gap insulating or semiconductor materials. An ultra-low RA of <0.4 ?ohm-cm2 in combination with a MR of 14%, low magnetostriction, and a low Hin value of about 20 Oe is achieved with a composite spacer of the present invention. The Cu layer thickness is from 0.1 to 10 Angstroms and the MgO thickness is from 5 to 20 Angstroms in spacer configurations including Cu/MgO/Cu, and MgO/Cu/MgO.

Abstract: A TAMR (Thermal Assisted Magnetic Recording) write head uses the energy of optical-laser generated plasmons in a plasmon generator to locally heat a magnetic recording medium and reduce its coercivity and magnetic anisotropy. To enable the TAMR head to operate most effectively, the antenna is formed in three portions, a wide portion of uniform horizontal area, a tapered portion tapering towards the ABS of the write head and a narrow tip extending from the tapered portion to the ABS. The wide portion enhances coupling of optical radiation from a waveguide to surface plasmons generated within the generator, the tapered portion condenses and focuses the plasmons as they propagate towards the ABS and the narrow tip further focuses the surface plasmon field at the medium surface.

Abstract: Systems and methods to achieve a circuit for driving one or more infrared transmitter LEDs with temperature compensation have been disclosed. In a preferred embodiment of the invention the circuit has been applied for a rain sensing system. The junction temperature of the LED is measured and compensated by adjusting the driver current of a voltage-to-current converter driving the LED. The LED junction temperature is measured by comparing the difference in the forward diode voltage at different current densities. This voltage difference is extracted when switching the drive currents between different constant values. The measurement results are converted to digital values, which are used by a buffered dual ladder resistive DAC structure to adjust the drive current to temperature variations.

Abstract: Systems and methods are disclosed for x-y tables wherein rolling elements of rolling-element bearings are transferring electrical energy between a fixed part of the x-y table and a movable part of the x-y table. The electrical energy transferred could be power to electrical devices as well as signals to and from devices on the movable part of the x-y table. Electrically conducting rolling elements are moving on electrically conducting grooves on the fixed and movable part of the x-y table. Conductor tracks on the fixed and movable part are connected to the grooves and to devices on the movable platform. In a preferred embodiment of the invention the x-y table is part of a camera wherein linear motors, preferably with integrated position sensing, are moving the x-y table back to a home position in case of a dislocation due to a mechanical shock. The invention allows an exact and fast positioning of an x-y table without requiring a flexible cable.

Abstract: An audio device (200) includes a first and second ICs (210) and (250) and a substrate (205). The first IC includes a sigma-delta, A/D converter (218) operable to convert an analog signal (234) into a pulse density modulated signal (236). A pulse density width modulator encoder (222) is operable to encode the PDM signal into a PDWM signal (244). The PDWM has short and long pulse widths defining first and second bit levels. The leading edges of each pulse bounds each pulse period. The second IC (250) includes a means (254) to receive the PDWM signal, an edge detector (304) operable to detect the leading pulse edges of the PDWM signal, a time-averaging circuit (308) operable to calculate each pulse period from the leading pulse edges and to generate a sample pulse (120) at near the midpoint of each pulse period, and a latch (312) operable to sample and hold the PDWM signal at the sample pulse to decode a PDM signal (278).

Abstract: A PMR writer is disclosed wherein a magnetic assist layer (MAL) made of an anisotropic (?Ku) or (+Ku) magnetic material is formed along a main pole trailing side to optimize the vertical magnetic field and field gradient at the air bearing surface. A Ru seed layer is formed between the main pole and (?Ku) MAL to induce a hard axis direction toward the main pole. A (?Ku) MAL is preferably comprised of hcp-CoIr while CoPt and FePt are examples of a (+Ku) MAL. The MAL has a down-track thickness from 5 to 20 nm, a width equal to the track width in a cross-track direction, and extends 100 to 500 nm in a direction toward a back end of the main pole. As a result, flux leakage from the main pole to trailing shield is reduced and aerial density is increased. A method for fabricating the PMR writer is provided.

Abstract: A method of forming a write pole in a PMR head is disclosed that involves forming an opening in a mold forming layer. A conformal Ru seed layer is formed within the opening and on a top surface. An auxiliary layer made of CoFeNi or alloys thereof is formed as a conformal layer on the seed layer. All or part of the auxiliary layer is removed in an electroplating solution by applying a (?) current or voltage during an activation step that is controlled by activation time. Thereafter, a magnetic material is electroplated with a (+) current to fill the opening and preferably has the same CoFeNi composition as the auxiliary layer. The method avoids Ru oxidation that causes poor adhesion to CoFeNi, and elevated surfactant levels that lead to write pole impurities. Voids in the plated material are significantly reduced by forming a seed layer surface with improved wettability.

Abstract: An array of SMT MRAM cells has a read reference circuit that provides a reference current that is the sum of a minimum current through a reference SMT MRAM cell programmed with a maximum resistance and a maximum current through an reference SMT MRAM cell programmed with a minimum resistance. The reference current forms an average reference voltage at the reference input of a sense amplifier for reading a data state from selected SMT MRAM cells of the array such that the reference SMT MRAM cells will not be disturbed during a read operation. The read reference circuit compensates for current mismatching in the reference current caused by a second order non matching effect.

Abstract: Digital miniature cameras and methods to manufacture thereof have been achieved. Said miniature cameras having an adjustable focusing device are intended to be used as a built-in modules in hand-held consumer electronic devices, such as e.g. mobile phones and PDAs. The cameras invented have a very small size and produce high-quality pictures. Glue is used to hold different parts together and to seal the joints. The lens is glued in the final stage of the manufacturing line, thus providing the focus setting and the sealing of the cavity that covers the image sensor. A glob top is used to cover and seal the image processor. Said glob top serves two different purposes, first, to distribute the heat away from the sensor and, second, to lock the frame, together with the lens house, into a printed circuit board. In one embodiment a cavity PCB is used to “bury” the sensor of the camera, thus reducing the overall height required.

Abstract: A spin transfer oscillator (STO) structure is disclosed that includes two assist layers with perpendicular magnetic anisotropy (PMA) to enable a field generation layer (FGL) to achieve an oscillation state at lower current density for MAMR applications. In one embodiment, the STO is formed between a main pole and write shield and the FGL has a synthetic anti-ferromagnetic structure. The STO configuration may be represented by seed layer/spin injection layer (SIL)/spacer/PMA layer 1/FGL/spacer/PMA layer 2/capping layer. The spacer may be Cu for giant magnetoresistive (GMR) devices or a metal oxide for tunneling magnetoresistive (TMR) devices. Alternatively, the FGL is a single ferromagnetic layer and the second PMA assist layer has a synthetic structure including two PMA layers with magnetic moment in opposite directions in a seed layer/SIL/spacer/PMA assist 1/FGL/spacer/PMA assist 2/capping layer configuration. SIL and PMA assist layers are laminates of (CoFe/Ni)x or the like.