Abstract: A system and method for processing stroke-based handwriting data for the purposes of automatically scoring and clustering the handwritten data to form letter prototypes. The present invention includes a method for processing digitized stroke-based handwriting data of known character strings, where each of the character strings is represented by a plurality of mathematical feature vectors. In this method, each one of the plurality of feature vectors is labelled as corresponding to a particular character in the character strings. A trajectory is then formed for each one of the plurality of feature vectors labelled as corresponding to a particular character. After the trajectories are formed, a distance value is calculated for each pair of trajectories corresponding to the particular character using dynamic time warping method. The trajectories which are within a sufficiently small distance of each other are grouped to form a plurality of clusters.

Abstract: A servo pattern for use on a data storage surface that includes at least one track to minimize position error during positioning of a transducer over the data storage surface. The servo pattern includes a plurality of servo burst fields of constant amplitude for defining a centerline of the track and for determining the position of the transducer. According to the present invention, at least one servo burst field comprises N segments, where N.gtoreq.2, and each of the N segments is written with constant amplitude. The amplitude of the at least one servo burst field is then determined as a function of the amplitudes of the N segments.

Abstract: The present invention provides a microprocessor, the microprocessor having a substrate with a first and a second side, the first and second sides being on opposite sides of the substrate. The microprocessor includes decoupling capacitors on the first side of the substrate; cache circuitry on the first side of the substrate; logic circuitry on the second side of the substrate; and a signal carrying means including a carrier substrate and wire bonds for carrying signals between the logic and cache circuitry.

Abstract: The present invention provides a system and method for verifying an integrated circuit model. The model includes a plurality of net variables. The system and method comprises generating a plurality of tests for simulating the integrated circuit, precalculating a reduced model based upon the generated tests, and evaluating the reduced model. In a preferred embodiment, the present invention includes restricting the test that are generated. Then net invariants for the integrated circuit are generated by translating the restricted plurality of tests to a smaller set of possible values for the net variables. Thereafter, a minimization algorithm or procedure is utilized to minimize the logic used in the particular system based upon the latch constraints. This system produces a reduced model which reduces the amount of the integrated circuit that must be simulated thereby increasing the simulation speed thereof.

Abstract: A system and method for providing copper interconnect in a trench formed in a dielectric is disclosed. In one aspect, the method and system include providing a copper layer; removing a portion of the copper layer outside of the trench; annealing the copper layer; and providing a layer disposed above the copper layer. In another aspect, the method and system include providing a copper interconnect formed in a trench on a dielectric. The copper interconnect includes a copper layer disposed in the trench and a layer disposed above the copper layer. The copper layer has a bamboo structure at least one grain. The at least one grain has substantially one orientation.

Abstract: The present invention provides a method and system for locating available information in a network environment by a user in a node. In a system aspect, within a node in the network, the present invention includes a network sniffer and an access sniffer. The access sniffer includes an access element and an access interface. The access element preferably includes a memory and a database. The access element accesses the network sniffer and filters out unavailable information by using information such as address and port numbers gathered by the network sniffer. Unavailable information includes information which is non-public or beyond the privilege level of the particular user. The access element evaluates data streams which are public information to determine if the data streams meet a predetermined criteria. If the data streams meet the predetermined criteria, then the data is saved in the database. The access element transfers only the information available to the particular user to the access interface.

Abstract: A method and system in accordance with the present invention provides a mechanism that would dynamically change the backing factor. The backing factor is the amount of time needed to ensure that the I/O interface can stay ahead of the host interface. A method and system for providing a high performance control unit to provide for optimal matching of first and second interfaces comprises calculating a backing factor based upon minimal memory contention, optimal data rate and minimal rotational delay, and determining whether a particular result has been achieved. The method and system further includes calculating a new backing factor based upon current and projected data rates if the desired result has not been achieved. In a preferred embodiment, the initial backing factor is calculated assuming no memory contention, the best possible data rate for both the I/O and host interface and no rotational delay.

Abstract: System and method aspects for avoiding data corruption during data transfer in a disk array environment are described. In a circuit aspect, an integrity checker includes counting logic for counting fields in the data being transferred. The integrity checker further includes comparison logic for comparing a constant value and a value in a predetermined field of data being transferred. Combinational logic is further included and coupled to the comparison logic and counting logic, wherein when the comparison logic results in a miscompare and the counting logic is at a predetermined count value, the integrity checker circuit aborts data transfer. In a method aspect, the method includes providing an integrity checker at an interface to an array of disk drives, and performing data validity determinations on data passing across the interface with the integrity checker, wherein invalid data is not transferred.

Abstract: The present invention is a method and system for improving resource utilization in a connection management system. The present invention alleviates the resource contention and resource under-utilization problems, and avoids the problem of contamination from the late arrival of delayed packets to a new connection which utilizes the same resources used in a preview connection. The method includes transferring data by using the connection resources from the server; determining if an error occurred during the transfer of data; if an error is not detected, returning the connection resources to the server; and if an error is detected, indicating the existence of the error with a status bit and waiting a predetermined period of time prior to returning the connection resources to the server.

Abstract: A method and system for providing direct execution of a serializing instruction in a processor is disclosed. The processor has the serializing instruction and a nonserializing instruction. The processor includes execution logic having a pipeline for executing the nonserializing instruction. The processor also includes logic separate from the execution logic for executing the serializing instruction. The method and system include recognizing the serializing instruction, recognizing the nonserializing instruction, providing the nonserializing instruction to the execution logic, and providing the serializing instruction to the separate logic. The serializing instruction is executed without providing the serializing instruction to the pipeline.

Abstract: A method and apparatus for holding, grinding and polishing a die include a platform (10), a boss (20) on the platform, and a shielding structure (30) attached to at least one of the platform (10) and the boss (20). The boss (20) is configured for supporting a packaged (42) die (41) to be ground and polished and has a supporting topography to accommodate at least one package and lead configuration. The shielding structure (30) is configured to protect such a packaged (42) die (41) from physical and electrical damage when supported on the boss (20).

Abstract: Method and system aspects for increasing throughput in a WLAN are provided. In a method aspect, a packet is transmitted from a first end station in the WLAN, the packet including an indication of a next end station in a chain of end stations having data ready for transmission in the WLAN. The method further includes transferring control of access before a predetermined time period has been exceeded to the next end station in the chain of end stations based upon the indicator. In addition, the method includes maintaining access to the network for a plurality of cooperating end stations established through continuous indication of the next end station in the chain of end stations without exceeding a maximum access time.

Abstract: A method for manipulating image data in a digital image capture device includes forming two or more image processors, and providing the two or more image processors in the digital image capture device. The method further includes linking the two or more image processors to form an image processing chain, the image processing chain capable of manipulating image data in sequential and serial manners.In a system aspect, the system includes a digital image capture device, the digital image capture device capable of processing digital image data through two or more image processors. The system further includes a central processing unit within the digital image capture device and capable of linking the two or more image processors to form an image processing chain, wherein the image processing chain manipulates the digital image data in sequential and serial manners.

Abstract: A noninvasive infrared spectrometer which includes an infrared detector system for measuring the intensity, wavelength, and time varying nature of infrared energy emanating from deep layers within a body. Before detection, the energy emanating from deep within the body passes through layers of that body in the presence of a natural or induced thermal gradient. The measured infrared energy is processed into an absorption spectra and then into a concentration of at least one constituent of the body which concentration may be strongly dependent on the depth into the body. In one embodiment the temperature gradient is induced by chilling the surface of the body to provide a clearer indication of the infrared absorption levels of the deeper constituents. Other embodiments describe the sequential or simultaneous heating and cooling of the heterogenous body to induce and capture the transient infrared absorption spectral information.

Abstract: Aspects for self bootstrapping word-line driver circuitry are provided. In a circuit aspect, a word-line driver circuit for a memory cell in a semiconductor memory includes a signal input means, the signal input means comprising a first plurality of transistors, the first plurality of transistors receiving an input voltage signal higher than a voltage supply signal of the semiconductor memory. The circuit further includes a signal output means, the signal output means comprising a second plurality of transistors coupled to the first plurality of transistors and providing an output drive signal sufficient for the memory cell.

Abstract: A system and method for providing a memory cell on a semiconductor is disclosed. In one aspect, the method and system include providing at least one gate stack on the semiconductor, depositing at least one spacer, and providing at least one source implant in the semiconductor. The at least one gate stack has an edge. A portion of the at least one spacer is disposed along the edge of the at least one gate stack. In another aspect, the method and system include providing at least one gate stack on the semiconductor, providing a first junction implant in the semiconductor, depositing at least one spacer, and providing a second junction implant in the semiconductor after the at least one spacer is deposited. The at least one gate stack has an edge. A portion of the at least one spacer is disposed at the edge of the at least one gate stack.

Abstract: A method and system is disclosed for accelerating a user interface on a display of an image capture unit. The image capture unit includes a plurality of image files for providing a plurality of images. In a first aspect, the method and system comprise selecting an image based upon a scrolling method and providing a predetermined number of speculation buffers. The method and system include organizing the predetermined number of speculation buffers based upon the selected image so as to assign each of the predetermined number of speculation buffers to store one of the plurality of images in response to the scrolling method. In a second aspect, the image capture unit operates in a plurality of modes The image capture unit also includes a plurality of input buffers which are utilized in one of the plurality of modes and are unutilized on at least one of the other of the plurality of modes.

Abstract: The present invention provides a device and a method for substantially minimizing defects on the surface of the interface of the stop layer and the oxide layer during manufacturing of a semiconductor device. A method according to the present invention for minimizing defects in a semiconductor device, the method including the steps of depositing a stop layer, the stop layer having a surface; bombarding the surface of the stop layer with N2 using a power of at least approximately 320 W; and depositing the oxide layer over the stop layer.

Abstract: A system and method for a telecommunications terminal system is disclosed. In one aspect, the method and system include providing a telecommunication device; and providing a back panel coupled to the telecommunication device. The back panel is for communicating with a plurality of devices and aiding in supporting the functions of each of the plurality of devices. Each of the plurality of devices is capable of being added to the system in a modular fashion. In another aspect, the method and system include providing a telecommunication device, a master unit coupled to the telecommunication device, and a slave unit. The master unit for communicating with a plurality of devices and aiding in supporting the functions of each of the plurality of devices, each of the plurality of devices capable of being added to the system in a modular fashion; and a slave unit coupled to the master unit for executing a plurality of applications.

Abstract: The present invention provides a method for accessing a plurality of gates in a random logic structure. The method includes the steps of providing a first address for a first line coupled to a gate, providing a second address for a second line coupled to the gate, providing at least one additional address for at least one additional line coupled to the gate, and accessing the gate at the intersection of the first, second, and additional addresses. A method for accessing random logic gates which allows for the testing of more logic gates than conventional methods and which is also faster than conventional methods has been disclosed. The method of the present invention provides a three or more dimensional (segmented) address for each gate which allows for the status of more gates to be specifically ascertained. This allows for more ease in testing, saving valuable time. The method of the present invention also has the added advantage of allowing repair of defective gates with redundant gates.