Patents Represented by Attorney, Agent or Law Firm Sawyer Law Group LLP
  • Patent number: 7352802
    Abstract: A low power DSL modem transmitter, suitable for incorporation in integrated DSLAM server line cards, transmits full power physical frames which include a control channel and a data field when data is available for transmission and physical frames having only a control channel or a control channel and a low power synchronization field when data is not available for transmission. And a method for controlling the total power dissipated in the integrated DSLAM by selectively restricting the flaw of data packets to the DSLs.
    Type: Grant
    Filed: September 28, 2005
    Date of Patent: April 1, 2008
    Assignee: International Business Machines Corporation
    Inventors: Gordon Taylor Davis, Jeffrey Haskell Derby, Evangelos Stavros Eleftheriou, Sedat Oelcer, Malcolm Scott Ware
  • Patent number: 7353387
    Abstract: Aspects for integrating encryption functionality into a database system are described. The aspects include providing at least two functions to support data encryption in a database system. The at least two functions are utilized within structured query language statements to preserve confidentiality of user-specified data in the database system.
    Type: Grant
    Filed: March 8, 2001
    Date of Patent: April 1, 2008
    Assignee: International Business Machines Corporation
    Inventors: Bruce Benfield, Constance Jane Nelin, Charles Daniel Wolfson
  • Patent number: 7351916
    Abstract: A thin circuit board includes a dielectric layer with at least one cavity formed on a surface thereof; a metal pad formed in the cavity; at least one circuit layer formed on another surface of the dielectric layer; and a plurality of conductive vias formed in the dielectric layer to electrically connect the circuit layer to the metal pad. A build-up circuit structure is formed on the surface of the dielectric layer where the circuit layer is formed, and a conductive element is formed on a surface of the metal pad, so as to form a single-sided build-up circuit structure that prevents the use of a core board. Therefore, the thickness of the circuit board can be reduced and the impedance of the circuit board can also be reduced due to elimination of the use of plated through holes.
    Type: Grant
    Filed: December 5, 2005
    Date of Patent: April 1, 2008
    Assignee: Phoenix Precision Technology Corporation
    Inventor: Shih-Ping Hsu
  • Patent number: 7350621
    Abstract: Embodiments of ladders (22, 106) are disclosed which utilize a wheel (112) to allow users to transport these ladders easily by rolling along a surface without carrying the entire weight of the ladder. The wheel (112) are located in positions which do not interfere with the use of these ladders.
    Type: Grant
    Filed: October 14, 2005
    Date of Patent: April 1, 2008
    Assignee: Inovent, Inc.
    Inventor: Richard J. Abraham
  • Patent number: 7349498
    Abstract: A system and method is disclosed for evaluating a data group of oversampled bits to detect edge transitions and for improving use of information available from a sampled data while maintaining acceptable noise rejection. An edge detection system for receiving a serial data stream includes a sampler for collecting a sample pattern from the serial data stream, the sample pattern including a succession of a plurality of data samples from the data stream with the plurality of data samples including multiple samples during a bit time associated with the data stream; a memory, coupled to the sampler, for storing one or more successive sample patterns; and a correlator, coupled to the memory, for producing a sample condition signal using a set of predefined patterns by comparing the stored sampled patterns to the predefined patterns.
    Type: Grant
    Filed: October 7, 2002
    Date of Patent: March 25, 2008
    Assignee: International Business Machines Corporation
    Inventors: Hayden C Cranford, Jr., Vernon R. Norman, Martin L. Schmatz
  • Patent number: 7348911
    Abstract: Common mode management between a DAC, such as a current-steering DAC, and a transconductance filter in a high-frequency transmission system. In one aspect of the invention, a transmission circuit includes a DAC that provides an analog signal from an input digital signal, and a filter such as a transconductance filter connected to the DAC, the filter receiving the analog signal and filtering the analog signal for transmission. A common mode management circuit connected to the DAC and the transconductance filter provides common mode compatibility in the interface connecting the DAC and the transconductance filter.
    Type: Grant
    Filed: August 8, 2006
    Date of Patent: March 25, 2008
    Assignee: Atmel Corporation
    Inventor: Emmanuel Marais
  • Patent number: 7349544
    Abstract: A Radio Frequency based security system for providing security for wireless Local Area Networks (WLAN) that allows the creation and maintenance of arbitrarily shaped secure wireless access areas with boundaries around said wireless Local Area Network and prevents access to the said wireless LAN from outside the perimeter of the secure area. The system includes a plurality of perimeter Radio Frequency Sentry Devices (RFSDs) that are employed to establish the boundaries of said secure area around said wireless LAN. The wireless LAN being secured may be an industry standard IEEE 802.11a, 801.11b or 802.11g based wireless LAN or any other wireless LAN that uses packet based communication protocols. The said RFSDs may be stand-alone devices or they may be connected to a wired or wireless Local Area Network.
    Type: Grant
    Filed: September 21, 2004
    Date of Patent: March 25, 2008
    Assignee: Blueleaf LLC
    Inventor: Sameer Tiwari
  • Patent number: 7348621
    Abstract: A non-volatile memory cell and method of fabrication are provided. The non-volatile memory cell includes a substrate of a first conductivity type, a first dopant region of a second conductivity type in the substrate, a second dopant region of the first conductivity type in the first dopant region, a first isolation region overlaying a portion of the substrate, the first dopant region, and the second dopant region, a second isolation region overlaying another portion of the substrate, the first dopant region, and the second dopant region, a contact region of the first conductivity type in the second dopant region, the contact region extending between the first isolation region and the second isolation region and being more heavily doped than the second dopant region, a gate dielectric atop the first isolation region and a portion of the contact region, and a gate conductor atop the gate dielectric.
    Type: Grant
    Filed: February 10, 2006
    Date of Patent: March 25, 2008
    Assignee: Micrel, Inc.
    Inventor: Paul M. Moore
  • Patent number: 7344402
    Abstract: Component module insertion and removal protection in computer systems. In one aspect, a connector assembly for a component module includes a connector that receives the component module and receives power from a power selection circuit, and a module attachment mechanism operative to secure the component module to the connector when a movable member is in an engaged position. In a disengaged position, the movable member allows the component module to be removed from the connector. When the movable member is moved from the engaged position, the state of a switch of the power selection circuit is changed, causing the power selection circuit to remove power from the connector and from at least a portion of a circuit board to which the connector is electrically coupled.
    Type: Grant
    Filed: March 16, 2006
    Date of Patent: March 18, 2008
    Assignee: Lenovo Pte. Ltd.
    Inventors: John K. Langgood, Thomas Francis Lewis, Kevin Michael Reinberg, Kevin Shayne Dwayne Vernon
  • Patent number: 7345921
    Abstract: Aspects for programming a nonvolatile electronic device include performing an initial verify step of a programming algorithm with an initial type of reference voltage value, and performing one or more subsequent verify steps in the programming algorithm with a second type of reference voltage value. Further included is utilizing a read reference voltage for the initial verify step, wherein desired programming is ensured for a cell that falls out of ideal distribution.
    Type: Grant
    Filed: May 12, 2005
    Date of Patent: March 18, 2008
    Assignee: Atmel Corporation
    Inventors: Stefano Surico, Simone Bartoli, Fabio Tassan Caser, Monica Marziani
  • Patent number: 7346609
    Abstract: A method generates hierarchical path index keys for single and multiple indexes with one scan of a document. Each data node of the document is scanned and matches to query nodes are identified. A data node matches a query node if the three conditions hold: if it is not the root step, there is a match for the query node in the previous step of the query; the data node matches the query node of the current step; and the edges of the data and query nodes match. A sub-tree of a data node can be skipped if the data node is not matched and its level is less than the fixed levels of the query. The matched data node is then placed in the match stacks corresponding to the match query nodes. The method uses transitivity properties among matching units to reduce the number of states that need to be tracked and to improve the evaluation of path expressions significantly.
    Type: Grant
    Filed: November 16, 2004
    Date of Patent: March 18, 2008
    Assignee: International Business Machines Corporation
    Inventors: Yao-Ching Stephen Chen, Irene Ching-Hua Liu, Demai Ni, Guogen Zhang, Qinghua Zou
  • Patent number: 7342308
    Abstract: Component stacking for increasing packing density in integrated circuit packages. In one aspect of the invention, an integrated circuit package includes a substrate, and a plurality of discrete components connected to the substrate and approximately forming a component layer parallel to and aligned with a surface area of the substrate. An integrated circuit die is positioned adjacent to the component layer such that a face of the die is substantially parallel to the surface area of the substrate. The face of the die is aligned with at least a portion of the component layer, and terminals of the die are connected to the substrate.
    Type: Grant
    Filed: December 20, 2005
    Date of Patent: March 11, 2008
    Assignee: Atmel Corporation
    Inventor: Ken Lam
  • Patent number: 7340712
    Abstract: The present invention provides a system and method for providing a standard cell library for reduced leakage and improved performance. The standard cell library comprises at least two sets of threshold voltage cells. At least one of the sets includes non-mixed threshold voltage cells. At least one of the sets includes mixed threshold voltage cells. The mixed threshold voltage cells have at least one threshold voltage cell having a first threshold voltage and a second threshold voltage cell having a second threshold voltage. The first and second threshold voltages are different. The mixed threshold voltage cells have substantially the same footprint as the non-mixed threshold voltage cell.
    Type: Grant
    Filed: June 1, 2005
    Date of Patent: March 4, 2008
    Assignee: International Business Machines Corporation
    Inventor: Anthony Correale, Jr.
  • Patent number: 7340312
    Abstract: A method and apparatus for monitoring and control of a system is disclosed. The method and apparatus include providing a plurality of sensors, a table, and a network processor. The sensors monitor attributes of the system. The table includes a plurality of entries. Each of the entries indicates at least one action to be taken in response to a portion attributes having particular values. The network processor is coupled with the sensors and with the table. The network processor receives from the sensors a plurality of statuses for the attributes. The network processor further determines at least one entry of the entries to access based upon the statuses and accesses the at least one entry to determine a corresponding action.
    Type: Grant
    Filed: June 26, 2003
    Date of Patent: March 4, 2008
    Assignee: International Business Machines Corporation
    Inventor: Norman C. Strole
  • Patent number: 7340660
    Abstract: A method and system for testing a high-speed circuit is disclosed. The method and system include obtaining a high-speed statistical signature of the high-speed circuit using a conventional tester. The method and system further include comparing the high-speed statistical signature of the high-speed circuit to an expected signature. Consequently, it can be determined whether the high-speed circuit functions within the desired parameters.
    Type: Grant
    Filed: October 7, 2003
    Date of Patent: March 4, 2008
    Assignee: International Business Machines Corporation
    Inventors: Hayden C. Cranford, Jr., Vernon R. Norman, Martin L. Schmatz
  • Patent number: 7336542
    Abstract: A nonvolatile latch includes a memory element for storing an input data value. A write protect element is coupled to the memory element for utilizing a write protect signal to ensure the input data value stored by the memory element remains during a loss of a supply voltage to the latch.
    Type: Grant
    Filed: February 1, 2005
    Date of Patent: February 26, 2008
    Assignee: Atmel Corporation
    Inventor: Terje Saether
  • Patent number: 7336285
    Abstract: Aspects for maintaining and providing a calibrated color environment for display devices of a computer system. In an aspect of an exemplary method, the method includes determining relevant state data. The method further includes saving the relevant state data as calibration information for the calibrated color environment. The relevant state data includes information about a display that has an effect on color, such as a framebuffer driver state, a display driver state, and phospher characteristics of the display.
    Type: Grant
    Filed: January 17, 2006
    Date of Patent: February 26, 2008
    Assignee: Apple Inc.
    Inventors: Ian Hendry, David Hayward, John Calhoun, Eric Anderson
  • Patent number: 7333578
    Abstract: An input data sequence is sampled according to a sampling clock such that a first set of samples corresponds to data values and a second set of samples corresponds to edges between the data values. The phase error between data transitions in the input sequence and the sampled edges is determined based on amplitudes of the sampled edges. The sampling clock's phase is adjusted based on the determined phase error. Typically, the phase error is proportional to an amplitude of a sampled edge. Sampled edge amplitude values are added or subtracted, according to the direction of each transition about each edge to form an error value which indicates the amount phase error.
    Type: Grant
    Filed: May 22, 2001
    Date of Patent: February 19, 2008
    Assignee: The Board of Trustees of the Leland Stanford Junior University
    Inventors: Ramin Farjad-Rad, Mark Horowitz
  • Patent number: 7333389
    Abstract: An improved method and device for column decoding for flash memory devices utilizes a burst page with a length greater than the length of a logical page. When a misalignment of an initial address occurs, valid reads across logical page boundaries are possible. The memory device enters the wait state only when a read crosses a burst page boundary. This minimizes the amount of time in which the memory device enters the wait state. In the preferred embodiment, this is achieved with a different management of the control signals that feed the third level of a three-level decoding stage column decoder. Changes to the architecture or in the number of column decoder selectors are not required. The memory access time during synchronous reads is thus improved.
    Type: Grant
    Filed: May 11, 2005
    Date of Patent: February 19, 2008
    Assignee: Atmel Corporation
    Inventors: Stefano Sivero, Simone Bartoli, Fabio Tassan Caser, Riccardo Riva Reggiori
  • Patent number: 7330860
    Abstract: An automatic initial data load to a new table copy concurrently with active replication to existing table copies in an asynchronous replication group includes: initiating a data load of the new table copy; creating spill queue(s) at the new table copy; loading the data from a source table copy to the new table copy, where changes for the active table copies are applied during the loading, but changes to the new table copy are stored in a spill storage area; applying the changes in the spill storage area to the new table copy after the loading of the data is done; and removing the spill storage area after the changes have been applied to the new table copy. Thus, a new table copy is initialized into the replication group without requiring that replication be suspended at the source or any of the existing table copies during the initializing process.
    Type: Grant
    Filed: February 26, 2004
    Date of Patent: February 12, 2008
    Assignee: International Business Machines Corporation
    Inventors: Nicolas G. Adiba, Serge Bourbonnais, Elizabeth B. Hamel, Somil Kulkarni, Bruce G. Lindsay