Patents Represented by Attorney, Agent or Law Firm Schwegman, Lundberg, Woessner & Kluth, P.A.
  • Patent number: 8301300
    Abstract: A smart card personalization system maintains a database containing card issuer data format templates, card applications, card operating system commands, and personalization equipment specifications and provides a centralized interface of inputs and outputs to a card issuing process which dynamically adjusts to changes in the issuing process to easily permit a card issuer to change data formats, card applications, card operating systems and/or personalization equipment in a card issuing process. The system interfaces to any card issuer management system, manages the transfer of cardholder data and card applications to the particular personalization equipment used, and maintains statistics for real-time and off-line inquiries to support critical management and reporting functions. Furthermore, the system works with a variety of security methodologies to prevent fraud.
    Type: Grant
    Filed: October 12, 1999
    Date of Patent: October 30, 2012
    Assignee: Card Technology Corporation
    Inventors: David R. Tushie, William W. Haeuser
  • Patent number: 7797236
    Abstract: A method and apparatus for collecting information about an event in which a user accesses the Internet through the system of a first Internet Service Provider with whom the user does not have an account. The apparatus includes a first server that creates a record of the user's Internet usage and sends the record to a second server. The second server collects records from a plurality of Internet Service Providers and forwards the records to a third server on a regular basis. The third server processes the data in the plurality of records and generates a report showing how much money the first Internet Service Provider is owed for allowing the user to access the Internet through the system of the first Internet Service Provider.
    Type: Grant
    Filed: December 10, 1999
    Date of Patent: September 14, 2010
    Assignee: iPass Inc.
    Inventors: Lynn Y. Liu, Xiaomei Guan, Michael E. Hayden, David Ling
  • Patent number: 7473956
    Abstract: Structures and methods for programmable array type logic and/or memory devices with asymmetrical low tunnel barrier intergate insulators are provided. The programmable array type logic and/or memory devices include non-volatile memory which has a first source/drain region and a second source/drain region separated by a channel region in a substrate. A floating gate opposing the channel region and is separated therefrom by a gate oxide. A control gate opposes the floating gate. The control gate is separated from the floating gate by an asymmetrical low tunnel barrier intergate insulator formed by atomic layer deposition. The asymmetrical low tunnel barrier intergate insulator includes a metal oxide insulator selected from the group consisting of Al2O3, Ta2O5, TiO2, ZrO2, Nb2O5, SrBi2Ta2O3, SrTiO3, PbTiO3, and PbZrO3.
    Type: Grant
    Filed: August 30, 2004
    Date of Patent: January 6, 2009
    Assignee: Micron Technology, Inc.
    Inventors: Jerome M. Eldridge, Kie Y. Ahn, Leonard Forbes
  • Patent number: 7421565
    Abstract: A method and apparatus to correctly compute a vector-gather, vector-operate (e.g., vector add), and vector-scatter sequence, particularly when elements of the vector may be redundantly presented, as with indirectly addressed vector operations. For an add operation, one vector register is loaded with the “add-in” values, and another vector register is loaded with address values of “add to” elements to be gathered from memory into a third vector register. If the vector of address values has a plurality of elements that point to the same memory address, the algorithm should add all the “add in” values from elements corresponding to the elements having the duplicated addresses. An indirectly addressed load performs the “gather” operation to load the “add to” values. A vector add operation then adds corresponding elements from the “add in” vector to the “add to” vector. An indirectly addressed store then performs the “scatter” operation to store the results.
    Type: Grant
    Filed: August 18, 2003
    Date of Patent: September 2, 2008
    Assignee: Cray Inc.
    Inventor: James R. Kohn
  • Patent number: 7364540
    Abstract: An implantable device and method for adjustably restricting a selected body lumen such as the urethra of a patient to treat urinary incontinence. The device includes an expandable element or membrane such as a balloon attached pressure-tightly to a flexible conduit at its forward end and includes a rear port portion containing an elastic septum and flow connected to the expandable element by a first passageway. The conduit contains a second passageway which allows it to be slid along an elongated guide probe initially inserted surgically into a patient's body adjacent the body lumen which is to be adjustably restricted. A suitable flowable material is injected from a syringe source into the device rear port sufficient to expand the membrane element and restrict the body lumen to the desired degree. The syringe and guide probe are removed and the skin incision is closed over the rear port end of the implanted device.
    Type: Grant
    Filed: January 5, 2000
    Date of Patent: April 29, 2008
    Assignee: Uromedica, Inc.
    Inventors: John H. Burton, Timothy C. Cook
  • Patent number: 7362169
    Abstract: In one embodiment, an amplifier to drive a load in response to an input voltage signal, the amplifier including a first amplifier to drive the load, a second amplifier, and a control sub-circuit to put the second amplifier into an active mode to drive the load when the output voltage of the first amplifier falls outside a voltage window, and to put the second amplifier into an inactive mode when the output voltage of the first amplifier falls within the voltage window. An embodiment also includes a switch to de-couple a capacitive impedance from the load after the second amplifier is put into its active mode, and to couple the capacitive impedance to the load when the output voltage of the first amplifier falls within the voltage window. Other embodiments are described and claimed.
    Type: Grant
    Filed: April 4, 2006
    Date of Patent: April 22, 2008
    Inventors: Gang Liu, Thomas Szepesi
  • Patent number: 7319935
    Abstract: A system and method to perform analysis on test results of multiple integrated circuits. Based on the analysis, the system and method display a wafer map having map indicators representing statistical values of the test results.
    Type: Grant
    Filed: February 12, 2003
    Date of Patent: January 15, 2008
    Assignee: Micron Technology, Inc.
    Inventors: Xueqing Sun, Mark Eyolfson, Chris Langworthy, Karl L. Major
  • Patent number: 7318490
    Abstract: Drill stem elements and connections are shown with advantages such as being mechanically robust. The absence of a side access window in a sonde housing is one design feature that provides robust mechanical properties. Further advantages of sonde housings include being easy to disassemble for access to the sonde unit, or for insertion of the sonde unit. In one embodiment, a cap portion is easily secured or removed using a small allen wrench, or a hammer and a punch. The cap portion is not substantially affected or tightened by rotation of the drill stem during a drilling operation. A further advantage includes the ability to remove cap portions and pull back flexible product such as polyethylene pipe from a small exit pit.
    Type: Grant
    Filed: October 26, 2006
    Date of Patent: January 15, 2008
    Assignee: IT Technologies, Inc
    Inventor: Michael Tjader
  • Patent number: 7317306
    Abstract: The present invention provides a nonlinear adaptive voltage positioning DC-DC converter method and apparatus that enable improved voltage transient response under changing current conditions for a load with known current draw characteristics. The invention in some embodiments provides that the nonlinear adaptive voltage positioning be adaptable or configurable to a specific, known current load range that comprises less than the full current range that may be provided by the DC-DC converter, to optimize voltage transient response for a particular known load.
    Type: Grant
    Filed: December 30, 1999
    Date of Patent: January 8, 2008
    Assignee: Intel Corporation
    Inventor: Robert J. Fite
  • Patent number: 7307277
    Abstract: A field effect transistor is provided which comprises a gate electrode, a source electrode, a drain electrode, at least one organic semiconducting layer, and a hole transport layer for transferring holes from said source and drain electrodes to said organic semiconducting layer, wherein said hole transport layer comprises a layered metal chalcogenide. Processes for depositing a thin layer of a layered metal dichalcogenide on a substrate and for producing top gate structures on a layered metal chalcogenide layer in the manufacture of field effect transistors according to the invention are also provided.
    Type: Grant
    Filed: May 7, 2004
    Date of Patent: December 11, 2007
    Assignee: Cambridge University Technical Services Ltd.
    Inventors: Gitti Frey, Kieran John Reynolds, Henning Sirringhaus, Richard Henry Friend
  • Patent number: 7297254
    Abstract: Systems and methods for water extraction and purification are disclosed. In one embodiment of the invention, a system includes at least one water lifting unit that fluidly communicates with a groundwater source, and a gas generator that is fluidly coupled to the at least one water lifting unit to generate a gas that buoyantly moves water from the groundwater source to a water consumer.
    Type: Grant
    Filed: July 18, 2006
    Date of Patent: November 20, 2007
    Inventors: Michael J. Harrington, Katherine Reinleitner
  • Patent number: 7288819
    Abstract: One aspect of the present subject matter relates to a partially depleted silicon-on-insulator structure. The structure includes a well region formed above an oxide insulation layer. In various embodiments, the well region is a multilayer epitaxy that includes a silicon germanium (Si—Ge) layer. In various embodiments, the well region includes a number of recombination centers between the Si—Ge layer and the insulation layer. A source region, a drain region, a gate oxide layer, and a gate are formed. In various embodiments, the Si—Ge layer includes a number of recombination centers in the source/drain regions. In various embodiments, a metal silicide layer and a lateral metal Schottky layer are formed above the well region to contact the source region and the well region. Other aspects are provided herein.
    Type: Grant
    Filed: August 25, 2004
    Date of Patent: October 30, 2007
    Assignee: Micron Technology, Inc.
    Inventor: Arup Bhattacharyya
  • Patent number: 7286876
    Abstract: An apparatus and method for verifying capture by first and second pacing pulses in which an evoked response waveform recorded during a pacing event is compared with template waveforms representing capture by the first, second, and both pacing pulses. The evoked response is then classified as representing a type of capture represented by a template waveform if the evoked response waveform highly correlates with one template waveform and has correlation values with the other template waveforms within specified bounds.
    Type: Grant
    Filed: September 19, 2002
    Date of Patent: October 23, 2007
    Assignee: Cardiac Pacemakers, Inc.
    Inventors: David J. Yonce, David Ternes
  • Patent number: 7281866
    Abstract: A shunt voltage regulator for a processor is disposed on the processor package. The shunt voltage regulator responds to AC transients. One embodiment includes a DC power converter voltage regulator that is disposed off the processor package, and that is optimized for DC power conversion. Another embodiment includes a method of improving fabrication yield for a packaged processor.
    Type: Grant
    Filed: December 30, 2003
    Date of Patent: October 16, 2007
    Assignee: Intel Corporation
    Inventors: Michael T. Zhang, Michael W. Eisele, Robert T. Carroll, William B. Pohlman, Kenneth A. Ostrom
  • Patent number: 7281338
    Abstract: Slide mounting tools are disclosed, including a magnetic slide mounting tool having at least one magnet for mounting a slide to a surface. In one embodiment, a first section of a slide can be magnetically coupled to the slide mounting tool and installed on a stationary component. In one embodiment, at least one magnet is oriented substantially vertically on the slide mounting tool for magnetic coupling with the first section of the slide during installation of the section on edge against a vertical surface. The magnetic mounting tool thus allows, for the first time, a user to not only magnetically couple a stationary component section of virtually any type of slide to a stationary component, but provides a design that allows an extension slide to be extended while clamped to the stationary component, thus allowing a single user to align, clamp, extend and install a stationary component section of a slide without any outside assistance.
    Type: Grant
    Filed: September 30, 2004
    Date of Patent: October 16, 2007
    Assignee: NPZ Inc.
    Inventors: Neil Ziegmann, Jeff Ziegmann
  • Patent number: 7281813
    Abstract: A safety vest is sized to be worn by a human, wherein the vest has a front and back and left and right sides each having a shoulder portion. An EL strip is provided on each side of the vest extending from the bottom of the vest upwards toward the shoulder portion. A power source is supported by the vest and connected to the EL lamp strips to supply electrical energy to the strips so that they emit EL light, wherein the EL light emitted by the EL strip is a safety yellow color, and wherein other portions of the vest are a safety orange color. Further safety articles of clothing and devices are also described.
    Type: Grant
    Filed: August 31, 2006
    Date of Patent: October 16, 2007
    Assignee: Safe Lites, LLC
    Inventors: John Golle, Aaron Golle
  • Patent number: 7276442
    Abstract: A method for depositing metal on a semiconductor device having a substrate, an exposed first surface, and an exposed second surface is provided. Metal ions are deposited on the exposed first surface and on the exposed second layer by applying a first voltage between the substrate and an anode in the presence of an electrolytic bath, and metal ions are removed from the exposed first surface by applying a second voltage between the substrate and the anode in the presence of the electrolytic bath. Other aspects and embodiments are provided herein.
    Type: Grant
    Filed: April 8, 2004
    Date of Patent: October 2, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Gurtej Sandhu Sandhu, Chris Chang Yu
  • Patent number: 7278152
    Abstract: An architecture for distributing digital information to subscriber units wherein selection from among multiple digital services is accomplished by transmitting a tuning command from a subscriber unit to an intermediate interface. The intermediate interface selects the desired service from a broadband network and transmits it to the subscriber unit over a bandwidth-constrained access line. The bandwidth-constrained access line may be implemented with existing infrastructure, yet the subscriber unit may access a wide variety of digital information available on the broadband network. Universal broadband access is thus provided at low cost. Output bandwidth of broadcast equipment may also be optimized.
    Type: Grant
    Filed: December 9, 1998
    Date of Patent: October 2, 2007
    Assignee: Irdeto Access, Inc.
    Inventor: R. Padmanabha Rao
  • Patent number: 7277754
    Abstract: An implantable cardiac rhythm management device is configured to remove pacing artifacts from recorded electrograms by a subtraction method. A template waveform representing a recorded pace without accompanying cardiac electrical activity is generated. Such a pacing pulse template is then aligned with the instant at which a pace is delivered and subtracted from the recorded electrogram in order to remove the pacing artifact.
    Type: Grant
    Filed: December 24, 2003
    Date of Patent: October 2, 2007
    Assignee: Cardiac Pacemakers, Inc.
    Inventors: Aaron McCabe, David J. Yonce
  • Patent number: D552541
    Type: Grant
    Filed: August 10, 2004
    Date of Patent: October 9, 2007
    Assignee: AB Connectors Limited
    Inventor: Jeff Gossett