Abstract: A circuit and method for producing a phase shifted quadrature signal (VOUT) from an in-phase signal (VIN). The in-phase signal (VIN) is applied to the control electrode of a voltage follower (121). The voltage follower (121) has a variable output resistance which combines with a capacitor (123) to delay the input signal (VIN) in accordance with the time constant formed by the variable output resistance and the capacitor (123). The variable output resistance is controlled by adjusting the bias current of the voltage follower (121) with a control signal.

Abstract: A current sense circuit (100) for providing an output signal (Iout) representative of a current signal (Id) flowing through a FET output device (101) comprises a first transistor (102) for providing an image current signal (I.sub.m) which is substantially proportional to the current signal flowing through the FET output device (101) until the drain-source voltage signal of the FET output device (101) is less than a predetermined voltage and a second transistor (104) coupled to a control electrode of the first transistor (102) and for coupling to the gate electrode of the FET output device (101). The first (102) and second (104) transistors are matched and have the same threshold voltages as that of the FET output device (101). The second transistor (104) provides a correction current signal (I.sub.c) when the drain-source voltage signal of the FET output device (101) is less than the predetermined voltage.

Abstract: An attribute on a netlist (31) is placed on a layout (33) to allow an automated approach for adding a feature to the layout (33) to be implemented. The netlist (31) or schematic diagram of a circuit is simulated on a Computer Aided Design (CAD) tool to verify circuit functionality. A layout tool (32) generates the layout (33) of the netlist (31). Adding a feature, for example, an extra implant to a source region of a device requires knowledge of device orientation not included in the layout (33). A Layout Versus Schematic (LVS) program (34) is run with the netlist (31) and the layout (33). Connectivity information from the LVS run is retrieved and placed in a connectivity mapping file (35). A mapping program (36) uses the connectivity mapping file (35) and the layout (33) to generate layers indicating and marking device orientation. The layers when added to the layout (33) produce an oriented layout (37).

Abstract: A squib ignitor circuit (20,40) reduces the probability of an accidental airbag deployment to greatly increase the safety of an automobile. A squib (24,28,44) operates at a voltage significantly higher than the squib ignitor circuit (20,40) to produce heat sufficient to ignite pyrotechnic material. Thus, a short condition to the squib (24,28,44) does not produce an inadvertent airbag deployment. The squib ignitor circuit (20,40) forms a conductive path through an inductor (23,43) via a first transistor (21,41) and a second transistor (22,42). The inductor (23,43) stores energy. The inductor (23,43) produces a voltage substantially greater than the voltage powering the squib ignitor circuit (20,40) when the conductive path is broken. The inductor (23,43) releases the stored energy to the squib (24,28,44) generating heat. A sequence (more than one time) of storing energy and releasing energy by the inductor (23,43) is required to generate heat sufficient to ignite pyrotechnic material by the squib (24,28,44).

Abstract: A common-mode sensing circuit (504) of a clocked differential amplifier (602) includes a refresh circuit (604) which precharges a capacitance during a first clock phase (P.sub.1) and discharges the capacitance to drive the outputs (514, 516) of the differential amplifier (602) to a desired common-mode voltage (V.sub.AGO) during a second clock phase, which increases the output loading during the second clock phase (P.sub.2). A load balancing circuit (606) selectively switches a load to the outputs (514, 516) during the first clock phase (P.sub.1) to match the load produced by the refresh circuit (604) during the second clock phase (P.sub.2).

Abstract: A method and circuit (10) for limiting current (I.sub.COIL) in a load (16). The current limiting circuit (10) includes a sensing circuit (12) having a current indicator output terminal (20) connected to an inverting input of a comparator (11). A reference voltage node (24) of a reference voltage generator (13) is connected to the non-inverting input of the comparator (11). The comparator (11) generates an output signal in accordance with the current flowing in the load (16). If an overcurrent condition exists, the signal from the comparator (11) disables a control circuit (14) which turns off the sensing circuit (12). With the control circuit (14) disabled and sensing circuit (14) off, the current (I.sub.COIL) is prevented from flowing through the load (16).

Abstract: A package assembly (70) for encapsulating and vertically surface mounting a semiconductor device such as an accelerometer includes a semiconductor device (40), a package (44) enclosing the semiconductor device, and a plurality of leads (16, 18) protruding from the package. The plurality of leads are formed from a common leadframe (10) and an internal portion of a first lead of the plurality of leads is offset from a common plane corresponding to the common leadframe prior to forming any of the plurality of leads. The offset lead increases the rigidity and vibration-resistance of the package assembly.

Abstract: An automobile airbag system for protecting human occupants of an automobile during an accident is provided. An airbag assembly comprises an airbag inflator assembly (45), an airbag (40), and a remote module (41). The remote module (41) includes a capacitor (42) and an integrated circuit (43) for coupling current through a squib (44) to ignite pyrotechnic material (46). The remote module (41) is formed as a plug which connects to the airbag (45) to simplify manufacture. Capacitor (42) provides energy to the squib (44) and switches for forming a conductive path that couples the current through the squib (44). The wiring between the integrated circuit (43) and the squib (44) is less than 3.0 centimeters to reduce electromagnetic radiation pick up.

Abstract: A non-inverting, inverting, delayed non-inverting, and delayed inverting non-overlapping clock signal is provided by a non-overlapping clock generator circuit (41, 61). The non-overlapping clock generator circuit (41, 61) increases time for circuit operation by minimizing delays between non-overlapping clock signals and simultaneously transitioning rising edges of clock signals. A non-overlapping clock generation circuit (41) comprises six NOR gates (43-48) and an inverter (42). Three NOR gates form a first delay line (43-45) and the remaining three NOR gates form a second delay line (46-48). The inverter (42) provides an inverted clock signal to the second delay line. A clock signal propagates through one delay line while the other delay line is non-responsive due to a feedback signal from the active delay line.

Abstract: A cell library (21) is optimized for specific operating characteristics. A stimulus file (23) is divided into a number of simulation run files. The simulation run files (27) are distributed to more than one computer work station so that the simulation of the cell occurs in parallel. The netlist (24) of each cell is parameterized to allow the cell to be changed and resimulated to better meet the specific operating characteristics. A cost function (32) is provided which uses the results of a transistor level simulation to calculate the quality of the cell design relative to the specific operating characteristics. Simulated annealing (34) is used to generate new simulation parameter values from a cost generated from the cost function (32). The cell is resimulated a number of times to optimize for the specific operating characteristics and the best design is retained for a new cell library (39). The process is repeated for each cell of the cell library (21).

Abstract: A voltage detector circuit (10) for detecting voltage levels of a digital data bitstream has an input terminal (20) coupled to receive the digital data bitstream. A first peak detector circuit (40) coupled to the input terminal detects a positive peak voltage, and provides a first peak signal. A first differential amplifier is coupled to the input terminal and further coupled to receive the first peak signal, for providing a first difference signal. A second peak detector circuit is coupled to receive the first difference signal from the first differential amplifier, for detecting a peak voltage in the first difference signal and for providing a second peak signal. The first peak signal indicates the value of logical 1 levels in the bitstream, and the second peak signal indicates the relative value of logical 0 levels in the bitstream with respect to the logical 1 levels.

Abstract: A non-breakdown triggered electrostatic discharge (ESD) protection circuit (11) having a voltage divider circuit and a SCR (22) protects an integrated circuit from an ESD event. The voltage divider includes a capacitor (17) and a resistor (18). The voltage divider connects to a pad of an integrated circuit and generates a trigger voltage for enabling the SCR (22) when an ESD event is applied to the pad. A worst case ESD voltage transient is used to calculate a trigger voltage for the SCR (22). The trigger voltage is selected at a voltage below where damage to the integrated circuit occurs. The SCR (22) is designed to have a turn on time constant that prevents normal signal levels from triggering the SCR (22).

Abstract: A wide bandwidth fast settling operational amplifier (71) comprises a first stage (72) and a second stage (73). The first stage attenuates a differential input signal applied to the operational amplifier (71). The second stage (73) provides all the gain of the operational amplifier (71). The first stage is a wide bandwidth stage having a differential input transistor pair (74,75) coupled in a voltage follower configuration. The differential input transistor pair (74,75) are degenerated by resistors (76,77) to reduce voltage gain and to lower an impedance coupled to the second stage (73). The first stage (72) is biased via a current source. The first stage (72) provides a reference voltage to the second stage that corresponds to and varies with an input common mode voltage. The reference voltage is used to bias a cascode stage in the second stage (73) to increase common mode range.

Abstract: A voltage and current reference circuit (11) having a low temperature coefficient is provided. The voltage and current reference circuit (11) minimizes component count to reduce area on an integrated circuit die. A bandgap voltage reference (12) produces a low temperature coefficient voltage. A voltage follower (13) is coupled to the bandgap voltage reference (12) that produces a reference voltage corresponding to a bandgap voltage. A temperature variant current from the bandgap voltage reference (12) is mirrored and provided to a first electrode of the voltage follower (13). A resistor (R4) is coupled between a power supply terminal and a second electrode of the voltage follower (13). The resistance of the resistor (R4) is selected to generate a current that cancels temperature dependencies of the temperature variant current. A current mirror circuit (14) receives a remaining portion of the temperature variant current and outputs a low temperature coefficient current.

Abstract: A method of generating power vectors to calculate power dissipation for a circuit is provided. The circuit includes both combinational logic and sequential logic circuits. The method includes removing all sequential logic circuits from the circuit. Boolean equations that describe the logical operation of the combinational logic of the circuit cells are generated. Power vectors are generated from the Boolean equations corresponding to internal and output transitions which dissipate power in the circuit. Redundant power vectors are then eliminated. The power vectors are then analyzed for "consistent" behavior with the sequential logic circuits. Operation of sequential logic circuits follow an ordered or defined sequence of events. Power vectors that are "inconsistent" with the operation of the sequential logic circuits are eliminated. The remaining power vectors are used to simulate the power dissipation of the circuit.

Abstract: Prior art differential track and hold amplifiers produce an error voltage when transitioning from a track mode to a hold mode. An error voltage limits the resolution of a track and hold amplifier. A first circuit (44) and a second circuit (45) couple a differential voltage to the storage capacitor. Control signals applied to the first and second circuits (44, 45) generate parasitic currents through parasitic capacitances which couple to a storage capacitor of a track and hold amplifier (41). The control signals applied to the first and second circuits (44, 45) are forced to transition an equal voltage magnitude to produce identical parasitic currents through the parasitic capacitance. Identical parasitic currents affect common mode voltage but do not change the differential voltage stored on the storage capacitor. A clamping circuit (50) clamps the voltage transition of the control signals to produce identical voltage transitions.

Abstract: An object of the present invention is to provide a scan test circuit for use in a semiconductor integrated circuit having a fewer package pins for scan tests.Scan mode setting and input/output of scan-in and scan-out data are performed by a single-bit bi-directional scan message signal.

Abstract: A linear differential gain stage (31) has a first input (32), a second input (33), a first output (34), and a second output (35). A differential input voltage is coupled to an input differential transistor pair (39,40). Voltage compensation circuits (53,54) cancel non-linearities due to the input differential transistor pair (39,40). Parasitic capacitance of the input differential transistor pair (39,40) couple current to the first and second inputs (32,33) due to voltage transitions at the first and second outputs (34,35). The current to the first and second inputs (32,33) is canceled by impedance compensation circuits (55,56) that provide an equal magnitude but opposite sign current. The result is an almost infinite input impedance to the linear differential gain stage (31).

Abstract: A data qualification circuit (11) comprises a comparator (28), a first threshold circuit (33), and a second threshold circuit (41). A differential input signal is applied to the data qualification circuit (11). A first threshold circuit (33) is enabled by a zero logic state at the output of comparator (28). The first threshold circuit (33) sets a one logic state threshold voltage which the differential input signal must overcome for the comparator (28) to generate a one logic state. A second threshold circuit (41) is enabled by a zero logic state at the output of comparator (28). The second threshold circuit (41) sets a zero logic state threshold voltage which the differential input signal must overcome for the comparator (28) to generate a zero logic state.

Abstract: A current sourcing output stage for a high voltage operational amplifier receives a low voltage input signal (V.sub.IN) and provides a high current output signal corresponding to the low voltage input signal at an output terminal (8). A first PNP transistor (Q1) is coupled between a voltage supply (V.sub.CC) and a plurality of cascaded PNP transistors (Q2, Q3, Q8-Q11) coupled to the output terminal (8). The base of the first PNP transistor (Q1) is coupled to receive the input signal (V.sub.IN) and the bases of the cascaded PNP transistors are coupled to receive different bias voltages A control circuit (Q5-Q7, R1-R5) is coupled to the voltage supply (V.sub.