Patents Represented by Attorney Shireen I. Bacon
-
Patent number: 7404067Abstract: Embodiments of an apparatus, system and method enhance the efficiency of processor resource utilization during instruction prefetching via one or more speculative threads. Renamer logic and a map table are utilized to perform filtering of instructions in a speculative thread instruction stream. The map table includes a yes-a-thing bit to indicate whether the associated physical register's content reflects the value that would be computed by the main thread. A thread progress beacon table is utilized to track relative progress of a main thread and a speculative helper thread. Based upon information in the thread progress beacon table, the main thread may effect termination of a helper thread that is not likely to provide a performance benefit for the main thread.Type: GrantFiled: September 8, 2003Date of Patent: July 22, 2008Assignee: Intel CorporationInventors: Tor M. Aamodt, Hong Wang, Per Hammarlund, John P. Shen, Steve Shih-wei Liao, Perry H. Wang
-
Patent number: 7181597Abstract: A system and method of managing processor instructions provides enhanced performance. The system and method provide for decoding a first instruction into a plurality of operations with a decoder. A first copy of the operations is passed from the decoder to a build engine associated with a trace cache. The system and method further provide for passing a second copy of the operation from the decoder directly to a back end allocation module such that the operations bypass the build engine and the allocation module is in a decoder reading state.Type: GrantFiled: August 31, 2005Date of Patent: February 20, 2007Assignee: Intel CorporationInventors: John Alan Miller, Stephan Jourdan
-
Patent number: 7171545Abstract: A mechanism, which supports predictive register cache allocation and entry, uses a counter look-up table to determine the potential significances of physical register references.Type: GrantFiled: December 30, 2003Date of Patent: January 30, 2007Assignee: Intel CorporationInventors: John P. Devale, Bryan P. Black, Edward A. Brekelbaum, Jeffrey P. Rupley, II
-
Patent number: 7143320Abstract: A method for increasing data throughput on a wireless local area network in the presence of intermittent interference. The method of one embodiment comprises receiving a data packet through a wireless channel. Quality of the wireless channel is evaluated. A packet error ratio (PER) value is calculated for the data packet. The PER value is checked as to whether it is within an acceptable level. A determination is made as to whether an intermittent noise is affecting the PER value.Type: GrantFiled: December 31, 2001Date of Patent: November 28, 2006Assignee: Intel CorporationInventor: Robert D. Cavin
-
Patent number: 7143404Abstract: A method for optimizing (re-structuring) data layout for 1) local or global variables and/or 2) fields of a structure or object and/or 3) function pointers in a virtual function table in a compiled program is based on profile feedback. A user, such as a software programmer, identifies one or more classes of data elements in an application that the user wishes to optimize. A method, which may be implemented in a software program such as a compiler, analyzes the profile for the designated data elements to determine, based on the application's temporal behavior, how to order the designated data elements in order to optimize data cache performance.Type: GrantFiled: March 31, 2003Date of Patent: November 28, 2006Assignee: Intel CorporationInventors: Mohammad R. Haghighat, David C. Sehr
-
Patent number: 7130990Abstract: A method and apparatus are provided for providing ready information to a scheduler. Dependence information is maintained in a relatively small map table, with potential loss of information when dependence information exceeds available space in the map table. Ready instructions are maintained, as space allows, in a select queue. Tags for scheduled instructions are maintained in a lookup queue, and dependency information for the scheduled instruction is maintained in an update queue, as space allows. Ready information for instructions in a scheduling window is updated based upon the information in the update queue. Loss of instruction information may occur, due to space limitations, at the map table, lookup queue, update queue, and/or select queue. Scheduling of lost instructions is handled by a lossy instruction handler.Type: GrantFiled: December 31, 2002Date of Patent: October 31, 2006Assignee: Intel CorporationInventors: Edward A. Brekelbaum, Bryan P. Black, Jeffrey P. Rupley, II
-
Patent number: 7114057Abstract: An article comprising an instruction stored on a storage medium. The instruction includes opcode field storing an opcode signal and an operand field storing an operand signal. The operand is compressed prior to being stored in the operand field.Type: GrantFiled: October 30, 2001Date of Patent: September 26, 2006Assignee: Intel CorporationInventors: Alan B. Kyker, Per Hammarlund, Chan Lee, Robert F. Krick, Hitesh Ahuja, William Alexander, Joseph Rohlman
-
Patent number: 7111154Abstract: Embodiments of an apparatus, method, and system provide for no-operation instruction (“NOP”) folding such that information regarding the presence of a NOP instruction in the instruction stream is folded into a buffer entry for another instruction. Information regarding a target NOP instruction is thus maintained in a buffer entry associated with an instruction other than the target NOP instruction. For at least one embodiment, NOP information is folded into entries of a re-order buffer.Type: GrantFiled: June 25, 2003Date of Patent: September 19, 2006Assignee: Intel CorporationInventors: Jeffrey P. Rupley, Edward A. Brekelbaum, Edward T. Grochowski
-
Patent number: 7035891Abstract: A method and system are provided for performing soft error detection for integer addition and subtraction operations without the use of redundant logic. For integer addition and subtraction, compensate logic produces a compensate value utilizing arithmetic logic unit (ALU) result and operands. The compensate value is validated by the validate logic against a predetermined value to determine whether a soft error has occurred. Such compensate logic and validate logic operate on the integer operands and on the result produced by the ALU without redundant carry-propagate hardware.Type: GrantFiled: August 27, 2002Date of Patent: April 25, 2006Assignee: Intel CorporationInventors: Sivakumar Makineni, Gautam B. Doshi
-
Patent number: 7032076Abstract: A method and apparatus to detect and filter out redundant cache line addresses in a prefetch input queue, and to adjust the detector window size dynamically according to the number of detector entries in the queue for the cache-to-memory controller bus. Detectors correspond to cache line addresses that may represent cache misses in various levels of cache memory.Type: GrantFiled: September 16, 2002Date of Patent: April 18, 2006Assignee: Intel CorporationInventors: Eric A. Sprangle, Anwar Q. Rohillah
-
Patent number: 6993540Abstract: In one embodiment a memory management method uses a third finger fetching pointer thread operating on memory objects distributed in a second memory space between a scan pointer thread and an allocation pointer thread to fetch objects in the second memory space prior to them being scanned. The fetching thread is moved to a next memory slot in the second memory space when the scanned memory slot does not hold a pointer to an object in the first memory space. The memory object is prefetched into a cache shared with an allocation pointer thread when the scanned memory slot holds a pointer to an object in the first space.Type: GrantFiled: December 20, 2002Date of Patent: January 31, 2006Assignee: Intel CorporationInventors: Richard L. Hudson, Hong Wang
-
Patent number: 6986010Abstract: A method and apparatus to speculatively allocate a combinable store request buffer for a cache lock operation by setting an extended lock indicator. The store request buffer is speculatively allocated and the load-lock micro-operation associated with the cache lock operation is sent to a replay loop. During the replay window, conflict detection processing is completed. When the load-lock micro-operation returns from replay, the store buffer is de-allocated if a conflict has been detected during the replay window.Type: GrantFiled: December 13, 2002Date of Patent: January 10, 2006Assignee: Intel CorporationInventors: Edwin R. Sutanto, Hoichi Cheong, Zhongru J. Lin, Jeffrey L. Nye
-
Patent number: 6957321Abstract: Instruction set extension using operand bearing no-operation (NOP) or other instructions. In one embodiment, an apparatus can execute a first instruction with an operand associated with a second instruction. The apparatus includes a decoder to identify an operand associated with the second instruction as being designated for the first instruction. An execution unit executes an operation indicated by the first instruction to operate on the operand associated with the second instruction. The second instruction may occur before or after the first instruction in the program sequence.Type: GrantFiled: June 19, 2002Date of Patent: October 18, 2005Assignee: Intel CorporationInventor: Gad S. Sheaffer
-
Patent number: 6950924Abstract: A system and method of managing processor instructions provides enhanced performance. The system and method provide for decoding a first instruction into a plurality of operations with a decoder. A first copy of the operations is passed from the decoder to a build engine associated with a trace cache. The system and method further provide for passing a second copy of the operation from the decoder directly to a back end allocation module such that the operations bypass the build engine and the allocation module is in a decoder reading state.Type: GrantFiled: January 2, 2002Date of Patent: September 27, 2005Assignee: Intel CorporationInventors: John Alan Miller, Stephan Jourdan
-
Patent number: 6925556Abstract: Methods, apparatuses, and systems are provided to determine a bootstrap processor. In an embodiment, the method determines a bootstrap processor from a plurality of operable processors in a fault tolerant multiprocessor system irrespective of an initialization time of a particular operable processor.Type: GrantFiled: February 14, 2001Date of Patent: August 2, 2005Assignee: Intel CorporationInventors: David Lawrence Hill, Frank Binns
-
Patent number: 6912709Abstract: The present invention provides a mechanism that facilitates speculative execution of instructions within software-pipelined loops. In accordance with one embodiment of the invention, a software-pipelined loop is initialized with a speculative instruction deactivated. At least one initiation interval of the software-pipelined loop is executed, and the speculative instruction is activated. Subsequent initiation intervals of the software-pipelined loop are then executed.Type: GrantFiled: December 29, 2000Date of Patent: June 28, 2005Assignee: Intel CorporationInventors: David A Helder, Kalyan Muthukumar
-
Patent number: 6904480Abstract: A system for generating transactions on a bus includes at least one instruction memory storing predefined bus stimuli instructions and at least one phase generator coupled between the bus and the instruction memory for providing signals to the bus in response to the instruction memory.Type: GrantFiled: December 17, 1997Date of Patent: June 7, 2005Assignee: Intel CorporationInventors: William A. Hobbs, Doug Boyce, Kenneth B. Oliver, Pierre M. Brasseur
-
Patent number: 6851013Abstract: A method of programming a memory. The method of one embodiment calls for sending a command to a memory device. The command requests the memory device to enter a program mode. A confirmation of the command is sent. A first address is sent to the memory device. A first packet of data is also sent to the memory device. The first packet of data is to be programmed at the first address. A first write signal is sent to the memory device. A second packet of data is sent to the memory device. A second write signal is sent to the memory device.Type: GrantFiled: December 15, 1999Date of Patent: February 1, 2005Assignee: Intel CorporationInventors: Peter T. Larsen, Lance W. Dover
-
Patent number: 6820250Abstract: A method is provided for processing nested loops that include a modulo-scheduled inner loop within an outer loop. The nested loop is scheduled to execute the epilog stage of the inner loop for a given iteration of the outer loop with the prolog stage of the inner loop for the next iteration of the outer loop. For one embodiment of the invention, this is accomplished by initializing an epilog counter for the inner loop to a value that bypasses draining the software pipeline. This causes the processor to exit the inner loop before it begins draining the inner loop pipeline. The inner loop pipeline is drained during the next iteration of the outer loop, while the inner loop pipeline fills for the next iteration of the outer loop.Type: GrantFiled: May 9, 2002Date of Patent: November 16, 2004Assignee: Intel CorporationInventors: Kalyan Muthukumar, Gautam B. Doshi
-
Patent number: 6784884Abstract: A method and apparatus for efficient parametric surface binning based on control points. One method of the present invention comprises transforming control points for a parametric surface. An extent of the control points is determined. Tiles interested by the extent are determined. The parametric surface is stored into the tiles.Type: GrantFiled: September 29, 2000Date of Patent: August 31, 2004Assignee: Intel CorporationInventor: Hsien-Cheng Emile Hsieh