Abstract: According to one embodiment of the invention, a method classifying a number of noun phrases in a first text passage and a second text passage into a number of classifications. The method also includes determining a similarity between a noun phrase from the first text passage and a noun phase from the second text passage for each of the noun phrases of a same classification. Additionally, a similarity between a sentence from the first text passage and a sentence from the second text passage is determined for each of the sentences in the first and second text passages based on similarities between the noun phrases. The method also includes determining a similarity between the first text passage and the second text passage based on a similarity between sentences.

Abstract: The latencies associated with cache misses or other long-latency instructions in a main thread are decreased through the use of a simultaneous helper thread. The helper thread is a speculative prefetch thread to perform a memory prefetch for the main thread. The instructions for the helper thread are dynamically incorporated into the main thread binary during post-pass operation of a compiler.

Abstract: Compiling a source code program for a heterogeneous multi-core processor having a first instruction sequencer, having a first instruction set architecture, an accelerator to the first instruction sequencer, wherein the accelerator comprises a heterogeneous resource with respect to the first instruction sequencer having a second instruction set architecture, the source code program having specified therein a region of source code for the first instruction set architecture of the processor and a region of source code for the second instruction set architecture of the processor.

Abstract: Methods and systems are provided for managing memory allocations and deallocations while in transactional code, including nested transactional code. The methods and systems manage transactional memory operations by using identifiers, such as sequence numbers, to handle memory management in transactions. The methods and systems also maintain lists of deferred actions to be performed at transaction abort and commit times. A number of memory management routines associated with one or more transactions examine the transaction sequence number of the current transaction, manipulate commit and/or undo logs, and set/use the transaction sequence number of an associated object, but are not so limited. The methods and systems provide for memory allocation and deallocations within transactional code while preserving transactional semantics. Other embodiments are described and claimed.

Abstract: A method for analyzing a set of spawning pairs, where each spawning pair identifies at least one speculative thread. The analysis may be practiced via software in a compiler, binary optimizer, standalone modeler, or the like. The analysis may include determining a predicted execution time for a sequence of program instructions, given the set of spawning pairs, for a target processor having a known number of thread units, where the target processor supports speculative multithreading. The method is further to select a spawning pair, according to a greedy approach, if the spawning pair provides a performance enhancement, in terms of decreased execution time due to increased parallelism, when the speculative thread is spawned during execution of a code sequence. Other embodiments are also described and claimed.

Abstract: A method and system are disclosed for performing trusted computing for blade devices, such as blade servers or other blade devices. The computing domain for the blade devices is managed by a chassis management logic module. Methods for performing blade capability authorization and optional blade authentication are provided. A method for performing blade device boot processing is also provided.

Abstract: The present invention provides a method and apparatus for executing a boundary check instruction that provides accelerated bound checking. The instruction can be used to determine whether an array address represents a null pointer, and whether an array index is less than zero or greater than the size of the array. Three extensions of a boundary check instruction are provided, with each performing a different combination of three boundary check comparisons. One comparison compares a first operand, which may contain the base address of an array, to zero. Another comparison evaluates the value of a second operand, which may contain an index offset, to determine if it is less than zero. The other comparison evaluates whether the value of the second operand is greater than or equal to a third operand. The third operand may indicate the size of an array. A trap is generated if any of the comparisons evaluates to true.

Abstract: A shared write back buffer for storing data from a data cache to be written back to memory. The shared write back buffer includes a plurality of ports, each port being associated with one of a plurality of processing units. All processing units in the plurality share the write back buffer. The shared write back buffer further includes a data register for storing data provided through the input ports, an address register for storing addresses associated with the data provided through the input ports, and a single output port for providing the data to the associated addresses in memory.

Abstract: The present invention provides software branch prediction filtering for a microprocessor. In one embodiment, a method for a software branch prediction filtering for a microprocessor includes determining whether a branch is “easy” to predict, and predicting the branch using software branch prediction if the branch is easy to predict. Otherwise (i.e., the branch is “hard” to predict), the branch is predicted using hardware branch prediction. Accordingly, more accurate but space-limited hardware branch prediction resources are conserved for hard-to-predict branches.

Abstract: The present invention provides a voice user interface with personality. In one embodiment, a method includes executing a voice user interface, and controlling the voice user interface to provide the voice user interface with a personality. The method includes selecting a prompt based on various context situations, such as a previously selected prompt and the user's experience with using the voice user interface.

Abstract: A method for selecting a candidate to mark as overwritable in the event of a cache miss while attempting to avoid a write back operation. The method includes associating a set of data with the cache access request, each datum of the set is associated with a way, then choosing an invalid way among the set. Where no invalid ways exist among the set, the next step is determining a way that is not most recently used among the set. Next, the method determines whether a shared resource is crowded. When the shared resource is not crowded, the not most recently used way is chosen as the candidate. Where the shared resource is crowded, the next step is to determine whether the not most recently used way differs from an associated source in the memory and where the not most recently used way is the same as an associated source in the memory, the not most recently used way is chosen as the candidate.