Patents Represented by Attorney Silicon Valley Patent Group
  • Patent number: 8074103
    Abstract: A computer is programmed to execute a diagnostic procedure either on a pre-set schedule or asynchronously in response to an event, such as an error message, or a user command. When executed, the diagnostic procedure automatically checks for integrity of one or more portions of data in the computer, to identify any failure(s). In some embodiments, the failure(s) may be displayed to a human, after revalidation to exclude any failure that no longer exists.
    Type: Grant
    Filed: October 17, 2008
    Date of Patent: December 6, 2011
    Assignee: Oracle International Corporation
    Inventors: Mark Dilman, Michael James Stewart, Wei-Ming Hu, Balasubrahmanyam Kuchibhotla, Margaret Susairai, Hubert Ken Sun
  • Patent number: 8068228
    Abstract: A structure that is located adjacent to a measurement target on a substrate is used to convert incident radiation from an optical metrology device to be in-plane with the measurement target. The structure may be, e.g., a grating or photonic crystal, and may include a waveguide between the structure and the measurement target. The in-plane light interacts with the measurement target and is reflected back to the structure, which converts the in-plane light to out-of-plane light that is received by the optical metrology device. The optical metrology device then uses the information from the received light to determine one or more desired parameters of the measurement target. Additional structures may be used to receive light that is transmitted through or scattered by the measurement target if desired.
    Type: Grant
    Filed: August 7, 2007
    Date of Patent: November 29, 2011
    Assignee: Nanometrics Incorporated
    Inventor: Ye Feng
  • Patent number: 8064246
    Abstract: A structure includes an electrically conductive material possessing spontaneous magnetization (“free magnet”) not in contact with an electrically resistive material possessing spontaneous magnetization (“pinned magnet”), and a spacer having free electrons to transfer spin between the electrically resistive material and the electrically conductive material. During operation, an existing direction of magnetization of the free magnet is changed to a new direction of magnetization, by a spin current generated by transfer of heat between at least the spacer and the pinned magnet. Thereafter, the new direction of magnetization of the free magnet is sensed. Many such structures are fabricated to have an easy axis of magnetic anisotropy in the free magnet, to implement memories that write data by transferring heat. Several such structures are fabricated to have an easy plane of magnetic anisotropy in the free magnet, to implement oscillators that generate an oscillating signal, on transfer of heat.
    Type: Grant
    Filed: December 8, 2010
    Date of Patent: November 22, 2011
    Inventor: John Casimir Slonczewski
  • Patent number: 8062910
    Abstract: A sample that is processed to remove a top layer, e.g., using chemical mechanical polishing or etching, is accurately measured using multiple models of the sample. The multiple models may be constrained based on a pre-processing measurement of the sample. By way of example, the multiple models of the sample may be linked in pairs, where one pair includes a model simulating the pre-processed sample and another model simulating the post-processed sample with a portion of the top layer remaining, i.e., under-processing. Another pair of linked models includes a model simulating the pre-processed sample and a model simulating the post-processing sample with the top layer removed, i.e., the correct amount of processing or over-processing. The underlying layers in the linked model pairs are constrained to have the same parameters. The modeling process may use a non-linear regression or libraries.
    Type: Grant
    Filed: November 13, 2008
    Date of Patent: November 22, 2011
    Assignee: Nanometrics Incorporated
    Inventors: Ye Feng, Zhuan Liu
  • Patent number: 8064200
    Abstract: Heat dissipating electronic components and circuitry in a communication chassis are cooled by moving air at least through a midplane, between two groups of channels that are laterally oriented relative to one another. In an illustrative embodiment, channels of one group are oriented vertically while channels of another group are oriented horizontally. Each channel, regardless of whether it is vertical or horizontal, is defined by space in the chassis between adjacent circuit boards. Circuit boards on one side of the midplane are electrically connected to circuit boards on the other side of the midplane by orthogonal connectors on the midplane. The midplane additionally has openings that enable movement of air between vertically-oriented channels and horizontally-oriented channels. Circuit boards of the two orientations are cooled by increasing air pressure in vertically-oriented channels or by decreasing air pressure in horizontally-oriented channels or both, depending on the embodiment.
    Type: Grant
    Filed: September 14, 2008
    Date of Patent: November 22, 2011
    Assignee: Cyan Optics, Inc.
    Inventors: Stephen J. West, Scott Pradels, Stephen S. Greer
  • Patent number: 8059931
    Abstract: A patch panel includes a rackmount cabinet, front and rear doors, a stepped front panel, and provision for inserting and securing a plurality of coupler cartridges. The stepped front panel has a recessed first portion and a second portion, where the second portion extends farther in a forward direction, e.g., towards the front door, than the recessed first portion. Traffic ports are positioned at the recessed first portion of the stepped front panel and monitor ports are positioned at the second portion of the front panel so that communication traffic cables inserted in the traffic ports are isolated from the monitoring ports. The communication traffic cables may be held in a cable management area that is at least partially defined by the recessed portion of the stepped front panel.
    Type: Grant
    Filed: May 6, 2009
    Date of Patent: November 15, 2011
    Assignee: Realm Communications Group, Inc.
    Inventor: John B. Russell
  • Patent number: 8054963
    Abstract: A method and system for providing call forwarding in an IP telephone network is disclosed. First, when a telephone number for a first telephone from a second telephone is dialed, the call is routing to a call manager. Call setup procedures with a BRG responsible for the first telephone are then initiated. The BRG then checks stored call forwarding profiles to determine whether there is an active call forwarding profile for the first telephone. The call is connected to the first telephone if an active call forwarding profile is not found. However, if an active call forwarding profile is found, the call forwarding information is sent to the call manager. The call is routed to at least a third telephone based on the call forwarding information.
    Type: Grant
    Filed: February 24, 2009
    Date of Patent: November 8, 2011
    Assignee: Shoretel, Inc.
    Inventors: Fen-Chung Kung, Jesse Eugene Russell, Anish Sankalia, Hopeton S Walker, Spencer C Wang
  • Patent number: 8051409
    Abstract: Techniques for monitoring memory accesses for computer programs are provided. A user can instruct a computer program to have one of more of its processes monitor memory accesses to a memory region. As memory accesses to the memory region occur, a log can be created that includes information concerning the memory accesses. The log can be analyzed in order to debug memory access bugs. Additionally, new processes can be spawned that monitor memory accesses in a way that is similar to existing processes.
    Type: Grant
    Filed: August 19, 2009
    Date of Patent: November 1, 2011
    Assignee: Oracle International Corporation
    Inventor: Kothanda Umamageswaran
  • Patent number: 8046161
    Abstract: A computer, for planning moves of freight automatically receives a plan containing a number of trips to be performed to move freight using vehicles, and partially releases only a portion of the plan for execution instead of releasing the entire plan. The plan portion that is released includes a subset of trips that are selected by the computer from among all trips in the entire plan. Thereafter, the computer simply repeats the just-described acts. Iteratively releasing portions of a plan allows the computer to be instructed to release early certain trips that are satisfactory. Trips that are sub-optimal are re-generated in a next version of the plan, based on changes in orders in the interim. The computer may also be instructed to release a trip even if sub-optimal, if its time-to-departure becomes less than an advance notice needed by a truckload service that is to execute the trip.
    Type: Grant
    Filed: June 30, 2005
    Date of Patent: October 25, 2011
    Assignee: Oracle International Corporation
    Inventors: Roy I. Peterkofsky, Hema Budaraju, Roger J. A. Goossens, Atul Kumar Srivastav, Vijay Pillarisetti
  • Patent number: 8045790
    Abstract: A method for processing wafers includes learning a first pattern at a de-skew site on a first wafer layer, saving the first patterns in a recipe for de-skewing wafers, learning a second pattern at the de-skew site a second wafer layer, and saving the second pattern in the same recipe for de-skewing wafers. Learning the first pattern may include determining a score of uniqueness for the first pattern. The method further includes finding the de-skew site on the second wafer layer using the first pattern before learning the second pattern. Finding the de-skew site includes determining a score of similarity between the first pattern and the second pattern. Learning the second pattern is performed when the score of similarity is less than a threshold value. A recipe for de-skewing wafers includes multiple patterns of a de-skew site of a wafer, wherein the patterns include a first pattern at the de-skew site on a first wafer layer and a second pattern at the de-skew site on a second wafer layer.
    Type: Grant
    Filed: September 10, 2008
    Date of Patent: October 25, 2011
    Assignee: Nanometrics Incorporated
    Inventors: Jian Zhou, Hua Chu
  • Patent number: 8040472
    Abstract: A multi-domain vertical alignment liquid crystal display that does not require physical features on the substrate (such as protrusions and ITO slits) is disclosed. Each pixel of the MVALCD is subdivided into color components, which are further divided into color dots. The polarity of the color dots are arranged so that fringe fields from adjacent color dots causes multiple liquid crystal domains in each color dot. Specifically, the color dots of a pixel are arranged so that each color dot of a first polarity has four neighboring pixels of a second polarity. Thus, a checkerboard pattern of polarities is formed. Furthermore, the checkerboard pattern is extended across multiple pixels in the MVALCD. In addition, many display unit include multiple pixel designs to improve color distribution or electrical distribution.
    Type: Grant
    Filed: June 25, 2009
    Date of Patent: October 18, 2011
    Assignee: Hiap L. Ong and Kyoritsu Optronics, Co., Ltd.
    Inventor: Hiap L. Ong
  • Patent number: 8037460
    Abstract: Software expressed in an intermediate level language is stored into a database and interpreted in a virtual machine in a database management system. A dynamic compilation process in the database management system asynchronously converts the software into native code when predetermined conditions are met. Thereafter, the compilation process persists the native code into the database. At the time of persisting the native code, the compilation process also stores in the database, an indication of any properties that are used in compilation of the native code. At run time, when the native code needs to be executed, the virtual machine checks if the indication stored in the database matches a new indication of the constants, and if they do the persisted code is executed or else the persisted code is invalidated. The persisted code is also invalidated when a new version of ILL software is stored into the database.
    Type: Grant
    Filed: January 26, 2007
    Date of Patent: October 11, 2011
    Assignee: Oracle International Corporation
    Inventors: Robert H. Lee, David Unietis, Mark Jungerman
  • Patent number: 8031278
    Abstract: A multi-domain vertical alignment liquid crystal display that does not require physical features on the substrate (such as protrusions and ITO slits) is disclosed. Each pixel of the MVA LCD is subdivided into color components, which are further divided into color dots. The drive component areas, i.e. where switching elements and storage capacitors are located, are converted to associated dots by adding an electrode that can be electrically biased. The voltage polarity of the color dots and associated dots are arranged so that fringe fields in each color dot causes multiple liquid crystal domains in each color dot. Specifically, the color dots and associated dots of a pixel are arranged so that associated dots have opposite polarity as compared to neighboring color dots.
    Type: Grant
    Filed: May 30, 2008
    Date of Patent: October 4, 2011
    Assignee: Hiap L. Ong and Kyoritsu Optronics Co., Ltd.
    Inventor: Hiap L. Ong
  • Patent number: 8031709
    Abstract: An integrated circuit has a hardware decoder that parses a frame to identify a type of encapsulation. The integrated circuit also has a number of hardware parsers, each parser being coupled to the decoder by an enable line. During packet processing, one of the parsers is enabled by the decoder, based on the value which identifies the encapsulation type. The enabled parser retrieves one or more attributes from the frame, depending on the encapsulation. The integrated circuit also has a register, coupled to each parser. The register holds the attributes retrieved by the parser. The integrated circuit also has a key generation hardware which creates a key, by concatenating from the attributes register, certain attributes that are pre-selected by a user for forming the key. The integrated circuit supplies the key to a memory to look up a set of user-specified actions to be performed on data in the frame.
    Type: Grant
    Filed: February 13, 2009
    Date of Patent: October 4, 2011
    Assignee: Applied Micro Circuits Corporation
    Inventor: Cedell A. Alexander, Jr.
  • Patent number: 8027037
    Abstract: In a measuring system, a method for evaluating parameters of a workpiece includes measuring a periodic structure, such as a grating, on the workpiece to produce image data. An orientation of features in the image data, produced by higher order diffractions from the periodic structure, is identified. An orientation of the periodic structure is determined based on the orientation of the features in the image data. The image data is then modified, based on the orientation of the periodic structure, to correlate with, and for comparison to, simulated image data to ascertain parameters of the workpiece. Alternatively, optical components in the measuring system, or the workpiece itself, are adjusted to provide a desired alignment between the optical components and the periodic structure. A microstructure on the workpiece may then be measured, and the resulting image data may be compared to the simulated image data to ascertain parameters of the microstructure.
    Type: Grant
    Filed: January 28, 2010
    Date of Patent: September 27, 2011
    Assignee: Nanometrics Incorporated
    Inventors: Mike Littau, Darren Forman, Chris Raymond, Steven Hummel
  • Patent number: 8027006
    Abstract: A multi-domain vertical alignment liquid crystal display that does not require physical features on the substrate (such as protrusions and ITO slits) is disclosed. Each pixel of the MVALCD is subdivided into color components, which are further divided into color dots. The polarity of the color dots are arranged so that fringe fields from adjacent color dots causes multiple liquid crystal domains in each color dot. Specifically, the color dots of a pixel are arranged so that each color dot of a first polarity has four neighboring pixels of a second polarity. Thus, a checkerboard pattern of polarities is formed. Furthermore, the checkerboard pattern is extended across multiple pixels in the MVALCD. In addition, many display unit include multiple pixel designs to improve color distribution or electrical distribution.
    Type: Grant
    Filed: June 26, 2009
    Date of Patent: September 27, 2011
    Assignees: Kyoritsu Optronics Inc., Ltd.
    Inventor: Hiap L. Ong
  • Patent number: 8026988
    Abstract: A multi-domain vertical alignment liquid crystal display that does not require physical features on the substrate (such as protrusions and ITO slits) is disclosed. Each pixel of the MVA LCD is subdivided into color components, which are further divided into color dots. The drive component areas, i.e. where switching elements and storage capacitors are located, are converted to associated dots by adding an electrode that can be electrically biased. The voltage polarity of the color dots and associated dots are arranged so that fringe fields in each color dot causes multiple liquid crystal domains in each color dot. Specifically, the color dots and associated dots of a pixel are arranged so that associated dots have opposite polarity as compared to neighboring color dots.
    Type: Grant
    Filed: May 30, 2008
    Date of Patent: September 27, 2011
    Assignee: Hiap L. Ong and Kyoritsu Optronics, Co., Ltd.
    Inventor: Hiap L. Ong
  • Patent number: 8018248
    Abstract: An integrated circuit includes a programmable logic device, a dedicated device, and an interface circuit between the two. The interface circuit can be easily modified to accommodate the different interface I/O demands of various dedicated devices that may be embedded into the integrated circuit. In one embodiment, the interface circuit may be implemented using a plurality of mask programmable uni-directional interface buffer circuits. The direction of any desired number of the interface buffer circuits can be reversed based on the needs of a desired dedicated device by re-routing the conductors in the interface buffer circuits in a single metal layer of the integrated circuit. In another embodiment, the interface circuit may be implemented using a hardware configurable bi-directional interface buffer circuit.
    Type: Grant
    Filed: September 21, 2006
    Date of Patent: September 13, 2011
    Assignee: QuickLogic Corporation
    Inventors: Ket-Chong Yap, Senani Gunaratna, Wilma Waiman Shiao
  • Patent number: 8018537
    Abstract: A multi-domain vertical alignment liquid crystal display that does not require physical features on the substrate (such as protrusions and ITO slits) is disclosed. Each pixel of the MVA LCD is subdivided into color components, which are further divided into color dots. The color components include polarized extension regions that extend between color dots of neighboring color components (and neighboring pixels). The voltage polarity of the color dots and polarized extension regions are arranged so that fringe fields in each color dot causes multiple liquid crystal domains in each color dot. Specifically, the color dots and polarity extension regions of the display are arranged so that neighboring polarized elements have opposite polarities.
    Type: Grant
    Filed: January 23, 2008
    Date of Patent: September 13, 2011
    Assignees: Kyoritsu Optronics Co., Ltd.
    Inventor: Hiap L. Ong
  • Patent number: 8018533
    Abstract: A method and system for adjusting selected colors of an image is presented. A chrominance adjustment system in accordance with one embodiment of the present invention, determines whether the color of the current pixel is near a selected color. When the color of the current pixel is near the selected color the chrominance adjustment system calculates a color specific chrominance adjustment factor based on the current color and the selected color and adjusts the color of the current pixel using the color specific chrominance adjustment factor.
    Type: Grant
    Filed: July 26, 2006
    Date of Patent: September 13, 2011
    Assignee: Huaya Microelectronics, Ltd
    Inventor: Ge Zhu