Abstract: Each bistable cell of a memory matrix is uniquely accessed through a row transistor and a column transistor connected in series between one node of the bistable cell and the data-in. During WRITE, a single row is accessed activating all of the gates on the row transistors of that row, and a single column is accessed activating all of the gates on the column transistors of that column. Only the addressed cell at the intersection of the accessed row and column has both the row and column transistors turned on establishing a conductive path to the data line. All of the remaining cells on the accessed row and column have only one of their access transistors turned on. The other access transistor of these partially accessed cells remains non-conductive. The data-in on the data line is either high ("1") or low ("0") driving the addressed cell into one of two storage states.
Abstract: An operational amplifier circuit comprised of complementary MOS transistors and having a bias section, a differential amplifier section, a level shift stage and an output stage, provides for frequency compensation using two capacitors. One capacitor, connected between the differential amplifier section and the output stage through a CMOS transmission gate that functions as a resistor, acts as the dominant pole of the transfer function. A second capacitor between the amplifier section output node and a level shift transistor, functions to remove the secondary poles in the transfer function and cause the dominant pole to occur at a higher frequency.
Abstract: A method for fabricating a complementary metal-oxide-silicon (CMOS) integrated circuit device by forming a composite layer of oxide and nitride on the surface of a silicon substrate defined into predetermined areas for the subsequent formation of transistors, masking the substrate to expose preselected areas for P-wells, ion implanting P-type material in the exposed areas to form P-wells so that a relatively high doping level is provided to a greater depth around composite areas within the P-wells areas and a relatively lower doping level is established under the composite layer areas with the P-wells. The ion implantation of P-type material may be accomplished in either a single stage or a two stage procedure.
September 20, 1979
Date of Patent:
December 22, 1981
American Microsystems, Inc.
Donald L. Wollesen, William Meuli, Philip S. Shiota
Abstract: An elliptic state variable filter uses switched capacitors controlled by an arrangement of switches that provides for a frequency response independent of stray capacitors in the circuit. The filter section comprises three integrating operational amplifiers connected in series, with a feedback connection between the output of the second operational amplifier and the circuit input to the first operational amplifier. Signals via a feed forward connection from the circuit input and the outputs of the first and second operational amplifier are summed by the third operational amplifier. Transmission zeros of the filter transfer function are realized independent of poles and with a feed forward arrangement which places them inherently on the unit circle and produces infinite loss at each zero frequency despite variations in capacitor ratios in the circuit.