Patents Represented by Attorney, Agent or Law Firm Skjerven Morrill MacPherson Franklin & Friel
  • Patent number: 6134285
    Abstract: In accordance with this invention, a data capture circuit of a data receiver captures data from a data stream of a data transmitter operating at a different phase or frequency from the system clock of the data receiver. In one embodiment, the data receiver determines the number of clock periods of a clock signal in a data period of the data stream. Specifically, a signal detection circuit receives a signal having a periodic and distinctive feature. The period of the periodic and distinctive feature is related to the data period by a fixed scaling factor. A counter counts the number of clock periods of the clock signal between a first occurrence of the periodic and distinctive feature and a second occurrence of the periodic and distinctive feature. A multiplier/divider circuit divides or multiples the content of the first counter by the scaling factor to determine the integer clock period count. The results of the multiply or divide is stored in a count register.
    Type: Grant
    Filed: May 28, 1997
    Date of Patent: October 17, 2000
    Assignee: Integrated Memory Logic, Inc.
    Inventor: Wei-Chi Lo
  • Patent number: 6132091
    Abstract: A two-axis stage assembly includes a generally planar horizontally mounted base plate; a stage plate generally parallel to the base plate, the stage plate having a first axis and second orthogonal axis; a set of spaced bearings depending from a bottom surface of said stage plate, the bearings each having an arcuate bottom surface in rocking contact with a facing support surface of the base plate; a joint attached to the bottom surface of the stage plate and pivotably mounting each bearing, the joint being positioned at the center of curvature of the arcuate bottom surface of the associated bearing; and where an axial movement of the stage plate rocks the bearing arcuate bottom surfaces with respect to the facing support surface of the base plate.
    Type: Grant
    Filed: November 17, 1998
    Date of Patent: October 17, 2000
    Assignee: Nikon Corporation
    Inventors: Martin E. Lee, Michael R. Sogard
  • Patent number: 6130517
    Abstract: A pair of complementary magnetic actuators controls a stage in a high-precision positioning instrument in a single coordinate direction. Additional pairs of complementary magnetic actuators can be used to provide control of the stage in other coordinate directions. A small current through the windings of both magnetic actuators provides a zero net force on the fine stage, thus maintaining the position of the fine stage. The small current used to control the fine stage minimizes the RMS power gain. By increasing the current in one magnetic actuator while decreasing the current in the other, a net force is generated for large accelerations of the stage. Control of the magnetic actuators is simplified by simultaneously increasing and decreasing the current through the windings of the complementary magnetic actuators prior to accelerating the stage. Additionally, a feedforward command can control the magnetic actuators to decrease the settling time of the system.
    Type: Grant
    Filed: February 12, 1998
    Date of Patent: October 10, 2000
    Assignee: Nikon Corporation
    Inventors: Bausan Yuan, Ting-Chien Teng
  • Patent number: 6131132
    Abstract: A high performance peripheral interface device is coupled to a computer via a computer bus and is coupled to a peripheral via a peripheral bus. To speed accessing of consecutively addressed data (the nth datum and the n+1th datum) from the peripheral, the interface device reads the n+1th datum from the peripheral: 1) before the computer has requested the n+1th datum from the interface device, and 2) while the computer is accessing the nth datum from the interface device.
    Type: Grant
    Filed: June 2, 1995
    Date of Patent: October 10, 2000
    Assignee: Cirrus Logic, Inc.
    Inventors: Kenneth C. Curt, Edward J. Chejlava, Jr., Anthony Kozaczuk
  • Patent number: 6130554
    Abstract: A programmable integrated circuit (see FIG. 13) includes a plurality of routing resources including collinearly extending routing wire segments and a test circuit for testing the integrity of the routing wire segments. The routing resource structures include a plurality of unprogrammed antifuses disposed between routing wire segments and a plurality of transistors disposed electrically in parallel with a corresponding respective one of the antifuses. The test circuit has a common node that may be coupled to a selected one of the routing resource structures for testing. In test mode, the test circuit detects whether a current flows through the selected routing resource structure and in response provides either a digital low value or a digital high value on an output node.
    Type: Grant
    Filed: September 17, 1997
    Date of Patent: October 10, 2000
    Assignee: QuickLogic Corporation
    Inventors: Paige A. Kolze, Andrew K. Chan, James A. Apland
  • Patent number: 6130813
    Abstract: For an electronic device having at least one power switch for each of two or more power sources such that the power switches can be selectively activated or deactivated depending on a signal supplied to them, a protection circuit having a current-sense circuit coupled to measure the current from the two or more power sources, and a latch for producing a switch deactivating signal and applying it to the switches in response to an over-current signal from the current-sense circuit can protect the switches and the electronic device from soft-short circuits and absolute short circuits. Bypass resistors coupled to the switches allow the electronic device to receive a small current ("pre-charge") before any of the switches are activated so that a comparator can test for the presence of various types of short circuits. Additionally, the precharging brings the electronic device to a higher voltage (as compared to no pre-charging) when one of the switches is activated, thereby helping to reduce in-rush currents.
    Type: Grant
    Filed: January 11, 1999
    Date of Patent: October 10, 2000
    Assignee: Dell U.S.A., L.P.
    Inventors: Barry K. Kates, John A. Cummings
  • Patent number: 6130539
    Abstract: An automatic gain control (AGC) system for use in line locators that detect concealed conductors is presented. The AGC system includes determining an AGC signal from a reference sensor and processing signals from one or more observed sensors utilizing the AGC signal. The reference sensor is located farther from the concealed conductor than the observed sensors. The AGC system can be implemented in analog form or can include a digital AGC determination in a microprocessor.
    Type: Grant
    Filed: August 19, 1998
    Date of Patent: October 10, 2000
    Assignee: Metrotech Corporation
    Inventor: Stevan Polak
  • Patent number: 6130490
    Abstract: A stage assembly for precision movement in the x and y-directions, especially adapted for use in electron beam lithography for holding a reticle. The stage assembly includes a vacuum enclosure in which a magnet plate structure moves in the y-direction under the influence of a linear motor with respect to the enclosure. Riding inside the magnet plate is the stage which holds the reticle and moves in both the x and y-directions. x-direction movement is accomplished by the stage moving under the influence of "turnaround motors" in the x-direction. A turnaround motor at each end of the stage is only on for a brief period in order to drive the stage relative to the magnet plate in the x-direction. Then the other turnaround motor at the other end of the stage turns on and stops the movement of the stage in that direction and drives it back in the opposite direction. Reaction forces used to move the stage are transferred to the ground independent of the electron beam column supports.
    Type: Grant
    Filed: April 6, 1999
    Date of Patent: October 10, 2000
    Assignee: Nikon Corporation
    Inventor: Martin E. Lee
  • Patent number: 6130563
    Abstract: An output driver circuit capable of driving its data output terminal to a digital logic level high, capable of driving its data output terminal to a digital logic level low, and capable of tristating its data output terminal has an output stage comprising a pullup transistor and a pulldown transistor. The two pullup and pull down transistors are coupled in series between two drive transistor circuits. In one aspect of the invention, the pullup and pulldown drive transistor circuits provide momentary low impedance connection of the pullup and pulldown transistors to the respective pullup and pulldown voltage sources during the initial switching waveforms of the digital signal. After the initial switching of the digital signal, the pullup and pulldown drive transistor circuits provide precise V.sub.OH and V.sub.OL voltage output levels and provide high impedance filtering of voltage supply line and ground line noise.
    Type: Grant
    Filed: September 10, 1997
    Date of Patent: October 10, 2000
    Assignee: Integrated Device Technology, Inc.
    Inventors: David J. Pilling, Raymond Chu
  • Patent number: 6131131
    Abstract: A conventional keyboard-style ACPI interface is greatly enhanced by the inclusion of a bi-directional hardware buffer and a special software protocol that allows multiple byte command and data messages to be sent in a burst fashion. The illustrative enhanced ACPI interface alleviates congestion in data transmission that results from the overhead incurred by transferring messages using multiple interrupts per message. An extended embedded controller includes a buffer for temporary storage of a plurality of data bytes and a program code for controlling data transfers to and from the buffer using a data handling technique that is ACPI-compliant.
    Type: Grant
    Filed: January 22, 1998
    Date of Patent: October 10, 2000
    Assignee: Dell U.S.A., L.P.
    Inventors: Robert Bassman, Anil Rao
  • Patent number: 6128226
    Abstract: A method for sensing a close to ground signal recieved from an array cell within a memory array includes the steps of providing a reference unit with a reference cell having a similar structure and a similar current path therethrough to that of the array cell, providing a timing unit with a timing cell having a similar structure and a similar current path therethrough to that of the array cell, discharging the array, the reference unit and the timing unit prior to charging them, generating a cell signal, a reference signal and a timing signal, respectively, upon charging, generating a read signal when the timing signal at least reaches a predefined voltage level and generating a sensing signal from the difference of the cell and reference signals once the read signal is generated. The reference unit has a reference capacitance which is a multiple of the expected capacitance of a bit line of the array and the timing unit has a predefined timing capacitance.
    Type: Grant
    Filed: February 4, 1999
    Date of Patent: October 3, 2000
    Assignees: Saifun Semiconductors Ltd., Tower Semiconductors Ltd.
    Inventors: Boaz Eitan, Oleg Dadashev
  • Patent number: 6127700
    Abstract: An insulated-gate field-effect transistor utilizes local threshold-adjust doping to control the voltage at which the transistor turns on. The local threshold-adjust doping is present along part, but not all, of the lateral extent of the channel. In the transistor structure, a channel zone laterally separates a pair of source/drain zones. The channel zone is formed with a main channel portion and a more heavily doped threshold channel portion that contains the local threshold-adjust doping. Gate dielectric material vertically separates the channel zone from an overlying gate electrode. The transistor is a long device in that the gate electrode is longer, preferably at least 50% longer, than the gate electrode of a minimum-sized transistor whose gate length is approximately the minimum feature size. The long-gate transistor is suitable for use in analog and high-voltage digital portions of a VLSI circuit.
    Type: Grant
    Filed: September 12, 1995
    Date of Patent: October 3, 2000
    Assignee: National Semiconductor Corporation
    Inventor: Constantin Bulucea
  • Patent number: 6127809
    Abstract: An adaptive battery charger for charging batteries used in portable electronic devices. The battery charger monitors power provided from an AC adapter to the portable electronic device, and adaptively utilizes all available power from the AC adapter for charging the batteries, both when the portable electronic device is off, and when it is in use. As the power required for the portable electronic device increases, the power provided to the batteries decreases. As the power required to power the portable electronic device decreases, the power available to charge the batteries increases.
    Type: Grant
    Filed: April 12, 1999
    Date of Patent: October 3, 2000
    Assignee: Dell USA, L.P.
    Inventors: Barry K. Kates, Edward P. Sheehan, Jr.
  • Patent number: 6127848
    Abstract: A circuit for voltage translation includes protection against gate oxide breakdown when translating a lower voltage signal into a higher voltage signal. An input signal inverter circuit inverts the lower voltage signal into an intermediate signal having an increased minimum value. By raising the maximum value of the intermediate signal to the voltage level of the higher voltage signal, an output signal inverter circuit produces a driving signal to drive an output stage. However, because the increased minimum value of the signal is maintained, the gate oxide breakdown voltage is not exceeded in the circuit. The circuit also includes a blocking transistor between the input signal inverter and the output signal inverter to prevent the larger driving signal from overloading the input inverter circuit.
    Type: Grant
    Filed: July 20, 1998
    Date of Patent: October 3, 2000
    Assignee: National Semiconductor Corporation
    Inventors: Joseph D. Wert, Richard L. Duncan
  • Patent number: 6127738
    Abstract: For electron beam wafer or mask processing, a registration mark is capacitively coupled to the top surface of an overlying resist layer on a substrate to form a voltage potential on the surface of the resist layer directly over the registration mark. The registration mark is directly connected to an electrical lead that produces an AC voltage on the registration mark, which is capacitively induced on the surface of the resist layer. Alternatively, the registration mark itself is capacitively coupled to a conductive plate placed on the bottom surface of the semiconductor substrate. An AC voltage is then applied to the conductive plate that induces a charge on the registration mark, which then capacitively induces a charge on the surface of the layer of resist. An electron beam scanning across the surface of the resist layer generates secondary electrons. The secondary electrons have a low energy and are affected by the voltage potential created at the surface of the resist layer.
    Type: Grant
    Filed: October 21, 1999
    Date of Patent: October 3, 2000
    Inventors: Tai-Hon Philip Chang, Hoseob Kim
  • Patent number: 6126798
    Abstract: An anode includes an anode cup, a membrane and ion source material, the anode cup and membrane forming an enclosure in which the ion source material is located. The anode cup includes a base section having a central aperture and the membrane also has a central aperture. A jet is passed through the central apertures of the base section of the anode cup and through the membrane allowing plating solution to be directed at the center of a wafer being electroplated.
    Type: Grant
    Filed: November 13, 1997
    Date of Patent: October 3, 2000
    Assignees: Novellus Systems, Inc., International Business Machines Corp.
    Inventors: Jonathan David Reid, Robert J. Contolini, John Owen Dukovic
  • Patent number: 6127261
    Abstract: A method of depositing a premetal dielectric layer involves deposition of a triple premetal dielectric layer in in-situ deposition in a single fabrication tool with each subsequent layer being deposited after a previous layer with no intervening handling step. Thus, no intervening cleaning steps or other intermediate steps are performed.
    Type: Grant
    Filed: November 16, 1995
    Date of Patent: October 3, 2000
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Minh Van Ngo, Darin A. Chan
  • Patent number: 6126512
    Abstract: An automated tracking and control system measures the lateral displacement of a moving belt, using non-contact sensing. The displacement signal is provided to an algorithm that adjusts the tilts of the belt pulleys and steers the belt laterally. Non-contact sensors include inductive proximity sensors, which respond to the metal belt but are immune to airborne slurry and other non-metallic debris in a hostile environment typical of wafer polishing. Other non-contact sensors include shielded optical sensors. Dual sensor configurations cancel response to non-lateral displacements. Instrumentation, such as tension sensors, cylinder pressure sensors, load transducers, and limit switches, provides input to the algorithm. Independent tension signals for each belt edge verify proper functioning of, e.g., pad conditioners. User-specified belt displacements, e.g.
    Type: Grant
    Filed: July 10, 1998
    Date of Patent: October 3, 2000
    Assignee: Aplex Inc.
    Inventors: Mike Chao, Tim H. Huynh, Chi Guo, Huey M. Tzeng
  • Patent number: 6128278
    Abstract: In a network switch, data received on an input connection can be transmitted on one or more output connections. When the switch receives a command to remove an output connection, the switch queues a marker cell in a queue cells to be transmitted on the output connection. The switch removes the connection when the switch reaches the marker cell as the switch traverses the queue to transmit the cells. A separate queue is provided for each input connection. For each input connection, the switch maintains a linked list of data structures each of which identifies an output connection which is to transmit data received on the input connection but for which the corresponding queue does not have data ready to be transmitted. When the queue gets data ready to be transmitted on all the output connections in the linked list, these output connections are moved to another linked list maintained for output connections for which there is a queue having data ready to be transmitted.
    Type: Grant
    Filed: August 30, 1996
    Date of Patent: October 3, 2000
    Assignee: MMC Networks, Inc.
    Inventors: Alexander Joffe, Ari Birger, Pravat Mishra
  • Patent number: D431451
    Type: Grant
    Filed: January 10, 2000
    Date of Patent: October 3, 2000
    Inventor: Kuo-Yung Kuo