Abstract: A ceramic or plastic body has a shelf comprising conductive traces. A semiconductor die is attached to the underside of the shelf, or to a base of the body. A void or voids in said shelf allows the passage of bond wires to couple the bond pads of the inferiorly positioned semiconductor die with said conductive traces. Manufacturable from ceramic, plastic, or any workable material, various described embodiments of the invention alleviate the need for a lead frame while being usable with a die having bond pads located either centrally or laterally. The invention can receive die of various dimensions without a change of design while allowing short bond wire lengths for each die size.

Abstract: The apparatus transfers a quantity of wafers from a first wafer boat to a second wafer boat. A wafer platform positioned beneath a wafer boat rises and transports the wafers to a pair of wafer grips which hold the wafers until the wafer platform is lowered and a second wafer about is in position to receive the wafers. The wafer platform is actuated by the negative pressure applied to alternating sides of a stage which divides a sealed cabinet into two portions. A vacuum is applied to alternating sides of the stage, while ambient air is introduced into the other side, causing the stage to move in the direction of lower pressure. The platform is affixed to the stage on at least two points.

Abstract: A low noise output buffer circuit that activates and deactivates the output by means of a two stage NAND and FET circuit. The two stages turn on sequentially but turn off simultaneously and minimizes the peak power supply current that normally appears during input and output switching operations.

Abstract: A method to anisotropically etch an oxide/silicide/poly sandwich structure on a silicon wafer substrate in-situ, that is, using a single parallel plate plasma reactor chamber and a single inert cathode. This method has an oxide etch step and a silicide/poly etch step, both of which are performed as plasma etch steps. The process allows a continuous etch to be applied without removing the wafer from the plasma reactor chamber. The fully etched sandwich structure has a vertical profile which has a controlled slope.

Abstract: Floating gates for EPROMs, E.sup.2 PROMs, Flash E.sup.2 PROMs, and other devices are texturized to provide more surface area than previous gate designs. Ruggedizing the upper surface of the floating gate causes texturization of an oxide-nitride-oxide layer formed superjacent to the floating gate, which causes texturization of the lower surface of the control gate formed thereupon resulting in increased coupling between the two gates. The oxide-nitride-oxide layer between the floating gate and control gate allows increased capacitance without allowing leakage of electrons between the two gates as would a layer of oxide which is normally used. The invention allows a smaller feature width, and therefore a higher density EPROM. Increased speed results from the reduced feature size.

Abstract: A dymanic random access memory device is constructed in which a first layer of semiconductive material is used to form series of transistors, using buried contacts on a silicon substrate. A dielectric is formed over the surface, and memory cells include a second layer of semiconductive material which is deposited over a dielectric. The active regions of the DRAM form a "dogbone" pattern, in which active regions exhibit elongate shapes in which each end of the elongate shape is wider than a center leg, and adjacent "dogbone" shapes are nested to form a compact pattern.

Abstract: A method of measuring the temperature of a sample or alternately, the pressure surrounding a sample, consists of using the photoacoustic effect to measure the resonant frequency of the sample. By measuring the resonant frequency of an object, which varies with changes in the temperature of the sample and the pressure surrounding the sample, a greater signal-to-noise ratio is achieved, thereby increasing the accuracy and robustness of the disclosed method over previous methods of measurement using the photoacoustic effect. To determine the desired parameter, the resulting resonant frequency is compared to values on like samples (or on the sample itself) under known environmental conditions.

Abstract: A CMOS transistor is fabricated by forming the n-wells with both phosphorus and arsenic implants. The arsenic, with its lower diffusion coefficient, tends to concentrate near the top surface of the n-wells, with the phosphorus penetrating sufficiently to define the n-wells at the desired depth. A boron channel stop implant is later applied without masking over the n-wells. Since the arsenic implant is concentrated near the surface, the arsenic impurities overcome the effects of the boron impurities.

Abstract: A pair of recirculating fans for semiconductor cleanroom use are stacked to allow each fan to service a smaller zone in the cleanroom than if the fans were placed side by side. Each fan controls the temperature, humidity, and particulate count for its own zone of the cleanroom, thereby allowing strict control of these parameters. The ductwork of the two fans are cross connected so that either fan can be maintained or repaired while the other fan services its own zone and the zone normally serviced by the off-line fan.

Abstract: A preferred embodiment of the invention is a poly input resistor located underneath, rather than alongside, an IC wirebond pad. This offers the advantages of a more efficient layout, more contacts connecting the pad to the resistor, a better contact configuration, and a larger, higher current resistor.

Abstract: An improved deionized water treatment system and method that consists of using a first and second water treatment train wherein the second train improves water quality by reducing particulate and total organic carbon by means of a reverse osmosis membrane assembly. The final pure water having particulate sizes less than one micron and a total organic carbon measure of less than one part per billion.

Abstract: Transfer molding equipment, used to encapsulate semiconductor die, is provided with clamps mounted to the mold base to position and align mold chases. Previous designs position and align the top and bottom mold chases using dowels on the mold base received in holes in the chases. The invention reduces the downtime of the mold equipment, and decreases the time required to replace the chases when a different package is to be produced.

Abstract: A process for forming within a masking layer a self-aligned annular opening having a width that is substantially narrower than the space width that can be created directly using the maximum resolution of available photolithography. The process involves the following steps: creation of a mask island using conventional photomasking and etching techniques, the perimeter of said island defining the inner perimeter of the perimetric annular opening; blanket deposition of a spacer layer, the thickness of which is equal to the desired width of the annular opening; a blanket deposition of a thick protective layer that is independently etchable over the spacer layer; planarization of the protection layer to or below the top of the spacer layer; and isotropically etching the exposed spacer layer to form a narrow annular opening exposing the substrate. At this point the exposed substrate may be trenched in order to isolate the area definedd by the island, or it may be fabricated in some other configuration.

Abstract: A DRAM cell having enhanced capacitance attributable to the use of a textured polycrystalline silicon storage-node capacitor plate. The present invention is particularly applicable to DRAM cells which employ a stacked-capacitor design, as such designs generally a conductively-doped polycrystalline silicon layer as the storage-node, or lower, capacitor plate. A poly texturization process imparts a three-dimensional texturized character to the upper surface of the storage-node plate. Texturization is accomplished by subjecting the storage-node plate layer to a wet oxidation step. Since oxidation at the crystal grain boundaries on the surface of the poly layer proceeds more rapidly than elsewhere, the surface becomes bumpy. When maximum texturization has been achieved, the overlying oxide is removed during a wet etch step.

Abstract: A tailored edge rate triggers a pulldown device which turns on a sense amplifier in a memory array to sense and amplify a voltage difference between two digit lines, facilitating a memory cell read operation. The tailored edge rate activates the pulldown device slowly at first, then quickly saturates it, to allow transistors in the sense amplifier to activate and quickly sense the digit lines without bouncing same.

Abstract: A technique for effectively doping a storage node capacitor plate constructed from low temperature deposited rugged polysilicon. A phosphorus silica glass is deposited prior polysilicon deposition and used primarily to uniformly diffuse n-type dopants into the subsequently deposited rugged poly capacitor plate. This doping technique eliminates the need for high temperature doping and will maintain the rugged surface in the poly of the capacitor plate.

Abstract: Apparatus to convert a single-mount SEM microscope stage into a multi-mount SEM microscope stage. The apparatus interfits onto the conventional center-aperture SEM microscope stage, and provides a mounting face having apertures for multiple-specimen mounts. The device is able to provide top or side views of the specimen with only a 45.degree. rotation of the microscope stage from its starting point.

Abstract: An integrated cirucuit is provided with a depletion mode filter capacitor, which reduces voltage spiking, while at the same time avoiding latchup problems caused by the capacitor. The depletion mode capacitor has a barrier layer which is doped to an opposite conductivity type as the integrated circuit's substrate, achieved by doping to provide an opposite difference from four valence electrons as the substrate. The barrier is formed as a part of a CMOS process, in a manner which avoids additional process steps. The capacitor is formed with one node connected to ground or substrate, and the other node directly to a power bus. The capacitor is located on open space available on the whole siliocn chip (memory as well as logic chip), particularly directly underneath the metal power bus to achieve an on-chip power bus decoupling capacitor wth capacitance in excess of 0.001 .mu.F.

Abstract: A dicing saw for semiconductors includes a defect detector which is used for stopping operation of the dicing saw when such operation would be adverse to the integrity of the work product (semiconductor dice). Infrared light from a light transducer is transmitted from a light transmitter to a detector at an opposite side of the saw's blade from the transmitter. Infrared light from a light transducer is also reflected from the dicing saw blade edge back to the transducer, permitting detection of reflected light along with the detection of light across the blade.

Abstract: An improved CMOS fabrication process which uses separate masking steps to pattern N-channel and P-channel transistor gates from a single layer of conductively-doped polycrystalline silicon (poly). The object of the improved process is to reduce the cost and improve the reliability and manufacturability of CMOS devices by dramatically reducing the number of photomasking steps required to fabricate transistors. By processing N-channel and P-channel devices separately, the number of photomasking steps required to fabricate complete CMOS circuitry in a single-polysilicon-layer or single-metal layer process can be reduced from eleven to eight. Starting with a substrate of P-type material, N-channel devices are formed first, with unetched poly left in the future P-channel regions until N-channel processing is complete. The improved CMOS process provides the following advantages over conventional process technology.