Abstract: An improved hard mask is provided to reduced pad erosion during semiconductor fabrication. The hard mask includes an etch stop layer between first and second hard mask layers.

Abstract: A dynamic random access memory is formed in a silicon chip in arrays of clusters, each of four cells in a single active area. Each active area is cross-shaped with vertical trenches at the four ends of the two crossbars. The central region of the active area where the two crossbars intersect serves as the common base region of the four transistors of the cluster. The top of the base region serves as a common drain for the four transistors and each transistor has a separate channel along the wall of its associated vertical trench that provides its storage capacitor. Each cluster includes a common bit line and four separate word-line contacts.

Abstract: A vertical trench in a silicon wafer for use in forming the storage capacitor of a DRAM is etched by reactive ion etching in a manner to have a profile that has multiple waists. This profile is obtained by varying the rate of flow of coolant in the base member on which the silicon wafer is supported during the reactive ion etching to vary the temperature of the silicon wafer during the etching. Alternatively, the multiple waists are achieved by either by varying the ratio of the different gases in the etching chamber or the total gas pressure in the chamber.

Abstract: A clock latency circuit, method and system is provided which allows the synchronization of data according to the rising and falling edges of a system clock.

Abstract: A random access memory cell having a trench capacitor formed below the surface of the substrate. A shallow trench isolation is provided to isolate the memory cell from other memory cells of a memory array. The shallow trench isolation includes a top surface raised above the substrate to reduce oxidation stress.

Abstract: Improved gap fill of narrow spaces is achieved by using a doped silicate glass having a dopant concentration in a bottom portion thereof which is greater than an amount which causes surface crystal growth and in an upper portion thereof having a lower dopant concentration such that the overall dopant concentration of the doped silicate glass is below that which causes surface crystal growth.

Abstract: A method for forming a pair of MOSFETs in different electrically isolated regions of a silicon substrate. Each one of the MOSFETs has a different gate oxide thickness. A first layer of silicon dioxide is grown to a predetermined thickness over the surface of the silicon substrate. One portion of the silicon dioxide layer is over a first isolated region and another portion of the silicon dioxide layer being over a second isolated region. An inorganic layer is formed over the silicon dioxide layer extending over the isolated regions of the silicon substrate. A first portion of the inorganic layer is over the first isolated regions and a second portion of the inorganic layer is over the second isolated regions. A photoresist layer is formed over the inorganic layer. The photoresist layer is patterned with a window over the first portion of the inorganic layer. The photoresist layer covers the second portion of the inorganic layer.

Abstract: A pair of memory cells for use in a DRAM are formed in a monocrystalline bulk portion of a silicon wafer by first forming a pair of vertical trenches spaced apart by a bulk portion of the wafer. After a dielectric layer is formed over the walls of each trench, the trenches are each filled with polycrystalline silicon. By a pair of recess forming and recess filling steps there is formed at the top of each trench a silicon region that was grown epitaxially with the intermediate bulk portion. Each epitaxial region is made to serve as the body of a separate transistor having its drain in the lower polysilicon fill of a trench, and its source in the monocrystalline bulk intermediate between the two epitaxial regions. The lower polysilicon fill of each trench is also made to serve as the storage node of the capacitor of each cell, with the bulk serving as the other plate of the capacitor.

Abstract: Reduction of gate-induced-drain-leakage in metal oxide semiconductor (MOS) devices is achieved by performing an anneal in a non-oxidizing ambient. In one embodiment, the anneal is performed in a argon and/or ammonia ambients after gate sidewall oxidation that forms the spacers.

Abstract: A method and circuit for producing an output current is provided. The method and circuit adds two currents with opposing temperature coefficients to produce such output current. A first one of the two currents, I.sub.1, is a scaled copy of current produced in a temperature compensated bandgap reference circuit. A second one of the two currents, I.sub.2, is derived from a temperature stable voltage produced by the bandgap circuit divided by a positive temperature coefficient resistance. The added currents, I.sub.1 +I.sub.2, provide the output current. The circuit includes a first circuit for producing: (i) a reference current having a positive temperature coefficient; and (ii) an output voltage at an output node substantially insensitive to variations in supply voltage and temperature over a predetermined range. The current source includes a second circuit connected to the output node for producing a first current derived from the bandgap reference current.

Abstract: A DRAM memory cell structure of a Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) and a stacked capacitor and a method for forming same facilitates low resistance contact between the source/drain of the transistor and a lower electrode of the capacitor. The method in its preferred embodiment uses platinum for the bottom electrode of the capacitor without the need for a diffusion barrier between it and a doped polysilicon plug used to contact the MOSFET. To this end, the formation of the contact is after the deposition of the high dielectric material, such as barium strontium titanate, used to form the dielectric of the capacitor. Also the bottom electrode of the capacitor is partially offset with respect to the polysilicon plug.

Abstract: Reduced variations in buried layer across the chip is provided. The reduction in variation is achieved by defining the top surface of the buried layer and then the lower surface of the buried layer. This results in improved control buried strap variations, thereby improving performance of the IC.

Abstract: A semiconductor memory in accordance with the present invention includes a data path including a plurality of hierarchical stages, each stage including a bit data rate which is different from the other stages. At least two prefetch circuits are disposed between the stages. The at least two prefetch circuits include at least two latches for receiving data bits and storing the data bits until a next stage in the hierarchy is capable of receiving the data bits. The at least two prefetch circuits are coupled between stages such that an overall data rate per stage between stages are substantially equal. Control signals control the at least two latches such that prefetch circuits maintain the overall data rate between the stages.

Abstract: A memory having an array of memory cells. The array includes a plurality of normal memory cells and a redundant memory cell. A decoder is provided for selecting an addressed one of the normal memory cells in response to an address and a normal condition signal and adapted address the redundant memory cell in response to the address and a fault condition signal. A redundant decoder is provided having an electronically erasable read-only-memory cell. The redundant decoder is adapted to produce the normal condition signal and to convert the normal condition signal into the fault condition signal when such read-only-memory cell is programmed into a fault condition. Each one of the read-only memory cells include a flash memory cell, a ferroelectric memory cell, or other such type of electronically erasable read-only memory cell which is substantially non-volatile and is able to retain its programmed state for a relatively long period of time.

Abstract: A method for reducing the formation of watermarks includes providing a semiconductor wafer and contacting the semiconductor wafer with a solution containing a watermark reducing amount of at least one cationic surfactant.

Abstract: A method for forming a electrically isolated semiconductor devices in a silicon body. A trench is formed in a selected region of the body. A barrier material is deposited over sidewalls of the trench. Portions of the barrier material are removed from a first sidewall portion of the trench to expose such first sidewall portion of the trench while leaving portions of such barrier material on a second sidewall portion of the trench to form a barrier layer thereon. A dielectric material is deposited in the trench, a portion of dielectric material being deposited on the exposed first sidewall portion of the trench and another portion of such deposited dielectric material being deposited on the barrier material. The dielectric material is annealed in an oxidizing environment to densify such deposited dielectric material, the barrier layer inhibiting oxidation of the said second sidewall portion of the trench.

Abstract: A method for forming integrated circuit conductors. The method includes the steps of placing in a reactive ion etching chamber a semiconductor body having disposed over a surface thereof: a metalization layer comprising an aluminum layer disposed between a pair of barrier metal layers; and, a photoresist layer disposed on a selected portion of a surface of an upper one of the pair of barrier layers. Radio frequency energy is inductively coupled into the chamber while silicon tetrachloride and chlorine are introduced into the chamber at rates selected to etch portions of the metalization layer exposed by the photoresist with aluminum having substantially vertical sidewalls. The silicon tetrachloride is introduced into the chamber at a rate in the range of 4 to 8 sccm. The rate of the chlorine is in the range of 50 sccm to 150 sccm. The chamber is at a pressure of about 12 milliTorr during the etching of the metalization layer.

Abstract: Disclosed is a semiconductor memory having a hierarchical bit line and/or word line architecture. In one embodiment, a memory having a hierarchical bit line architecture, particularly suitable for cells smaller than 8F.sup.2, includes a master bit line pair in each column, including first and second master bit lines with portions vertically spaced from one another. The first and second master bit lines twist with respect to one another in the vertical direction such that the first master bit line alternately overlies and underlies the second master bit line. A plurality of local bit line pairs in each column are coupled to memory cells, with at least one of the local bit lines coupled to a master bit line. In other embodiments, hierarchical word line configurations are disclosed including master word lines, sub-master word lines, and local word lines, electrically interconnected to one another via either switches, electrical contacts, or electrical circuits.

Abstract: A method of fabricating semiconductor chips includes the steps of optimizing a number of chips that geometrically fit on a wafer and maximizing chip yield for the wafer by considering chips located in a normally rejectable location and utilizing yield probability data for the chip in the normally rejectable locations to weight the probability of an acceptable chip such that if the probability is above a threshold value the chips are not rejected. This results in an increased chip yield for semiconductor wafers.

Abstract: A process for the manufacture of silicon integrated circuits uses a dual damascene metallization process with an organic intermetal dielectric (14). A pattern to be etched is first etched in a hard mask (16) without exposing the underlying intermetal dielectric (14) and then transferred into the intermetal dielectric (14) on an enlarged scale.