Abstract: Some embodiments of the invention provide a method of searching for a three-dimensional global path between first and second sets of routable elements in a region of a layout that has multiple layers. The method partitions the region into several sub-regions. It then performs a path search to identify a path between a first set of sub-regions that contains the first-set elements and a second set of sub-regions that contain a second-set element. When the method performing the path search, it explores expansions along Manhattan and non-Manhattan routing directions between the sub-regions on a plurality of layers.

Abstract: Some embodiments of the invention provide a method of specifying a cost function that represents the estimated distance between an external state and a set of states in a multi-state space that represents a region of a design layout. The method identifies a polygon that encloses the set of states. It then identifies vectors to project from the vertices of the polygon. Based on the projected vectors, the method identifies a set of distances that includes the distance between the polygon and each point in a set of points in the external state. The method then uses the identified set of distance to specify the cost function.

Abstract: A Method And Apparatus For Control of Rate-Distortion Tradeoff by Mode Selection in Video Encoders is Disclosed. The system of the present invention first selects a distortion value D near a desired distortion value. Next, the system determines a quantizer value Q using the selected distortion value D. The system then calculates a Lagrange multiplier lambda using the quantizer value Q. Using the selected Lagrange multiplier lambda and quantizer value Q, the system begins encoding pixelblocks. If the system detects a potential buffer overflow, then the system will increase the Lagrange multiplier lambda. If the Lagrange multiplier lambda exceeds a maximum lambda threshold then the system will increase the quantizer value Q. If the system detects a potential buffer underflow, then the system will decrease the Lagrange multiplier lambda. If the Lagrange multiplier lambda falls below a minimum lambda threshold then the system will decrease the quantizer value Q.

Abstract: Some embodiments of the invention provide an integrated-circuit chip that has a design based on a wiring model that allows at least a particular wiring layer to have more than one preferred wiring directions. Other embodiments provide a method of manufacturing an integrated circuit (“IC”) that has a plurality of wiring layers. The method specifies a layout of the IC by using a wiring model that specifies more than one preferred wiring direction for at least a region of a particular wiring layer. The method then uses the layout to fabricate the integrated circuit.

Abstract: A method and apparatus for performing nickel salicidation is disclosed. The nickel salicide process typically includes: forming a processed substrate including partially fabricated integrated circuit components and a silicon substrate; incorporating nitrogen into the processed substrate; depositing nickel onto the processed substrate; annealing the processed substrate so as to form nickel mono-silicide; removing the unreacted nickel; and performing a series procedures to complete integrated circuit fabrication. This nickel salicide process increases the annealing temperature range for which a continuous, thin nickel mono-silicide layer can be formed on silicon by salicidation. It also delays the onset of agglomeration of nickel mono-silicide thin-films to a higher annealing temperature. Moreover, this nickel salicide process delays the transformation from nickel mono-silicide to higher resistivity nickel di-silicide, to higher annealing temperature.

Abstract: Some embodiments of the invention provide a method of decomposing a region of an intergrated circuit (“IC”) layout. The region contains several routable elements. Based on the routable elements, the method defines a plurality of nodes in the region. It then triangulates the region based on the nodes. The method then uses the triangles to define routes in the region.

Abstract: The invention is directed towards method and apparatus that consider diagonal wiring in placement. Some embodiments of the invention are placers that use diagonal lines in calculating the costs of potential placement configurations. For instance, some embodiments estimate the wirelength cost of a placement configuration by (1) identifying, for each net in a net list, a bounding box that encloses all the circuit elements of the net, (2) computing an attribute of each bounding box by using a line that can be completely or partially diagonal, and (3) computing the wirelength cost estimate based on the computed attributes. To estimate the wirelength cost of different placement configurations, other embodiments construct connection graphs that model the net interconnect topologies. These connection graphs can have edges that are completely or partially diagonal. Other embodiments use diagonal lines to measure congestion costs of potential placement configurations.

Abstract: An apparatus comprising a substrate; and a platform elevated above the substrate and supported by curved flexures. The curvature of said flexures results substantially from variations in intrinsic residual stress within said flexures. In one embodiment the apparatus is a deformable mirror exhibiting low temperature-dependence, high stroke, high control resolution, large number of degrees of freedom, reduced pin count and small form-factor. Structures and methods of fabrication are disclosed that allow the elevation of mirror segments to remain substantially constant over a wide operating temperature range. Methods are also disclosed for integrating movable mirror segments with control and sense electronics to a produce small-form-factor deformable mirror.

Abstract: Some embodiments of the invention provide a method of decomposing a region of an intergrated circuit (“IC”) layout. The method defines several nodes in the region. The method then specifies a plurality of edges in the region. Each edge is between a pair of nodes, and some edges are neither perpendicular nor parallel to some of the edges. The method uses the edges to define routes in the region.

Abstract: Some embodiments of the invention provide a method of routing several nets in a region of a design layout. Each net includes a set of pins in the region. In some embodiments, the method partitions the region into several sub-regions that have a number of edges between them. The method (1) for each particular edge, identifies an edge-intersect cost based on a set of potential routes for the nets that intersect the particular edge, and (2) selects routes for the nets based on the computed edge-intersect costs. A potential route for a particular net traverses the set of sub-regions that contain the particular net's set of pins. Also, different embodiments identify different edge-intersect costs.

Abstract: Some embodiments of the invention provide a method of determining whether a set of routes can be geometrically embedded in a region according to a particular wiring model. The method identifies a congestion graph that has a set of edges, where at least two edges are neither orthogonal nor parallel. For each edge, the method identifies the set of routes that intersect the edge. It then determines whether any edge is overcongested.

Abstract: Some embodiments of the invention provide a method of expanding a path in a space with dimensional states. In some embodiments, the space includes a set of states and a transition map that specifies a set of states that can be reached from each particular state. The method identifies a first expansion for the path from a start state to a first destination state. It then specifies a first cost function that expresses the cost of the first expansion. The first cost function is defined over the destination state. The method also identifies a second expansion for the path from a first portion of the first destination state to a second destination state. From a portion of the first cost function that is defined over the first portion of the first destination state, the method computes a second cost function that specifies the cost of the second expansion.

Abstract: The present invention introduces methods of creating floor plans and placements for non Manhattan integrated circuits with existing electronic design automation tools. To create a floor plan, an existing Manhattan based floor planning tool is used. The die size for the floor plan is reduced to take into account the improved wiring density of non Manhattan wiring. A non Manhattan global router is then used on the floor plan to create pin placements. The floor plan may create a floor plan having circuit modules with beveled corners to take advantage of diagonal wiring. To create a placement, an existing Manhattan based placer is first used to create an initial placement. The initial placement is then processed by a non Manhattan aware post processor. The post processor performs local optimizations on the initial placement to improve the placement for a non Manhattan routed integrated circuit.

Abstract: A logic circuit employs a shunt peaked technique to enhance the switching speed of the circuit without an increase in power dissipation. A differential logic gate implements a digital circuit function. The shunt peaked logic circuit includes two resistive and two inductive elements. For each differential output line, a resistive element is coupled in series to an inductive element so as to couple the circuit power supply voltage to a differential output line. Under this configuration, the bandwidth of the logic circuit is increased without an increase in power consumption. The logic circuit may be implemented using CML or ECL logic. Techniques for improving large signal performance for active shunt-peaked circuits are also disclosed.

Abstract: Some embodiments of the invention cover the top of a flip chip IC with a conductive adhesive material. This material is used in place of a shielding metal can or plate in some embodiments, while it is used in conjunction with such metal can or plate in other embodiments of the invention. Also, some embodiments use a printing technique to coat the top of the flip chip with the conductive adhesive material. In some embodiments, the coating material is a silver paste.

Abstract: A synchronous circuit implements a bypass mode for use in conjunction with an inductive-capacitive (“LC”) buffer. The LC buffer receives differential conventional clock signals, and generates buffered differential conventional clock signals. A synchronous circuit, such as a latch, includes at least two clock receivers. The conventional clock signal is input to the first clock receiver, such as a transistor, and an auxiliary clock is input to a second clock receiver. The conventional clock signal provides timing for the synchronous circuit under a normal mode of operation, and the auxiliary clock signal provides timing for the synchronous circuit under a test mode of operation at a frequency lower than the conventional clock signal.

Abstract: Some embodiments of the invention provide a method for constructing a convex polygon that encloses a set of points in a region. This method identifies a first polygon that encloses the set of points. It then identifies a second polygon that encloses the set of points. The method then specifies the convex polygon as the intersection of the first and second polygons.

Abstract: A method for defining and producing a power grid structure of an IC that minimizes the area of the power grid structure area and the diagonal wiring blockage caused by the power grid structure while still meeting design constraints. A power grid planner is used to determine dimensions and locations of power grid components for each IC layer using a power grid formula, an objective for the power grid formula, a set of constraints, and a set of parameters. The method also includes processes of a power grid router, power grid verifier, and global signal router that are used iteratively with processes of the power grid planner to continually refine the dimensions and locations of the power grid components until the power grid structure meets design constraints and until global signal routing is successful on each layer of the IC.

Abstract: The invention is directed towards routing method and apparatus. Some embodiments provide a routing method that uses diagonal routes. This method routes several nets within a region of a circuit layout. Each net includes a set of pins in the region. The method initially partitions the region into several sub-regions. For each particular net in the region, the method then identifies a route that connects the sub-regions that contains a pin from the set of pins of the particular net. Some of the identified routes have edges that are at least partially diagonal.

Abstract: Some embodiments of the invention provide a method of routing nets in a region of a layout with multiple layers. The method defines a routing graph that has several of nodes on plurality of layers, where each node represents a sub-region on a layer. In the graph, there is a set of edges between the nodes on each layer. On one layer, there is at least one set of edges that are neither orthogonal nor parallel to a set of edges on another layer. The method uses this routing graph to identify routes.