Patents Represented by Attorney, Agent or Law Firm Stephen A. Gratton
  • Patent number: 7452391
    Abstract: Hydrogen generators and integrated hydrogen generator/fuel cells systems are operated by determining the condition of the hydrogen generator and the condition of the fuel to the hydrogen generator for selection of predetermined flow rates for each of the externally-provided raw materials. The processes of the invention can provide rapid transitions between hydrogen production rates while enabling enhanced efficiency and stability during transient operations.
    Type: Grant
    Filed: July 30, 2003
    Date of Patent: November 18, 2008
    Assignee: HyRadix Inc.
    Inventors: Bradley P. Russell, John R. Harness, Paul G. Blommel, Daniel R. Sioui, Suheil F. Abdo, Kurt M. Vanden Bussche, Robert J. Sanger
  • Patent number: 7449910
    Abstract: An interconnect for testing a semiconductor component includes a substrate, and interconnect contacts on the substrate configured to electrically engage component contacts on a semiconductor component. Each interconnect contact includes a compliant conductive layer formed as a conductive spring element. In addition, the complaint conductive layer includes a tip for engaging the component contact and a spring segment portion for resiliently supporting the tip. A method for fabricating the interconnect includes the steps of shaping the substrate, forming a conductive layer on a shaped portion of the substrate and removing at least some of the shaped portion. The shaped portion can comprise a raised step or dome, or a shaped recess in the substrate. The conductive layer can comprise a metal, a conductive polymer or a polymer tape can include a penetrating structure or penetrating particles.
    Type: Grant
    Filed: February 6, 2006
    Date of Patent: November 11, 2008
    Assignee: Micron Technology, Inc.
    Inventors: Kyle K. Kirby, Warren M. Farnworth
  • Patent number: 7432600
    Abstract: A system includes a semiconductor component having a base die and a secondary die flip chip mounted to the base die. The base die includes a set of stacking contacts for flip chip mounting the secondary die to the base die, and a set of interconnect contacts configured as an internal signal transmission system, and a physical structure for supporting a terminal contact system of the package component. The component also includes an encapsulant on the base die encapsulating the interconnect contacts, an underfill layer between the dice, and terminal contacts configured for flip chip mounting the package component to a supporting substrate.
    Type: Grant
    Filed: June 23, 2006
    Date of Patent: October 7, 2008
    Assignee: Micron Technology, Inc.
    Inventors: Dean A. Klein, Alan G. Wood, Trung Tri Doan
  • Patent number: 7432604
    Abstract: A semiconductor component includes a thinned semiconductor die having protective polymer layers on up to six surfaces. The component also includes contact bumps on the die embedded in a circuit side polymer layer, and terminal contacts on the contact bumps in a dense area array. A method for fabricating the component includes the steps of providing a substrate containing multiple dice, forming trenches on the substrate proximate to peripheral edges of the dice, and depositing a polymer material into the trenches. In addition, the method includes the steps of planarizing the back side of the substrate to contact the polymer filled trenches, and cutting through the polymer trenches to simulate the components from the substrate. Prior to the simulating step the components can be tested and burned-in while they remain on the substrate.
    Type: Grant
    Filed: August 15, 2005
    Date of Patent: October 7, 2008
    Assignee: Micron Technology, Inc.
    Inventors: Warren M. Farnworth, Alan G. Wood, Trung Tri Doan
  • Patent number: 7417325
    Abstract: A semiconductor component includes a thinned semiconductor die having protective polymer layers on up to six surfaces. The component also includes contact bumps on the die embedded in a circuit side polymer layer, and terminal contacts on the contact bumps in a dense area array. A method for fabricating the component includes the steps of providing a substrate containing multiple dice, forming trenches on the substrate proximate to peripheral edges of the dice, and depositing a polymer material into the trenches. In addition, the method includes the steps of planarizing the back side of the substrate to contact the polymer filled trenches, and cutting through the polymer trenches to singulate the components from the substrate. Prior to the singulating step the components can be tested and burned-in while they remain on the substrate.
    Type: Grant
    Filed: January 20, 2006
    Date of Patent: August 26, 2008
    Assignee: Micron Technology, Inc.
    Inventors: Warren M. Farnworth, Alan G. Wood, Trung Tri Doan
  • Patent number: 7409762
    Abstract: A method for fabricating an interconnect for testing a semiconductor component includes the steps of providing a substrate, and forming interconnect contacts on the substrate configured to electrically engage component contacts on the component. The interconnect contacts include flexible spring segments defined by grooves in the substrate, shaped openings in the substrate, or shaped portions of the substrate. The spring segments are configured to flex to exert spring forces on the component contacts, and to compensate for variations in the size or planarity of the component contacts. The interconnect can be configured to test wafer sized components, or to test die sized components.
    Type: Grant
    Filed: April 3, 2006
    Date of Patent: August 12, 2008
    Assignee: Micron Technology, Inc.
    Inventor: Kyle K. Kirby
  • Patent number: 7411304
    Abstract: An interconnect for testing a semiconductor component includes a substrate, and interconnect contacts on the substrate configured to electrically engage component contacts on a semiconductor component. Each interconnect contact includes a compliant conductive layer formed as a conductive spring element. In addition, the complaint conductive layer includes a tip for engaging the component contact and a spring segment portion for resiliently supporting the tip. A method for fabricating the interconnect includes the steps of shaping the substrate, forming a conductive layer on a shaped portion of the substrate and removing at least some of the shaped portion. The shaped portion can comprise a raised step or dome, or a shaped recess in the substrate. The conductive layer can comprise a metal, a conductive polymer or a polymer tape can include a penetrating structure or penetrating particles.
    Type: Grant
    Filed: January 6, 2005
    Date of Patent: August 12, 2008
    Assignee: Micron Technology, Inc.
    Inventors: Kyle K. Kirby, Warren M. Farnworth
  • Patent number: 7393770
    Abstract: A backside method for fabricating a semiconductor component with a conductive interconnect includes the step of providing a semiconductor substrate having a circuit side, a backside, and a substrate contact on the circuit side. The method also includes the steps of forming a substrate opening from the backside to the substrate contact, and then bonding the conductive interconnect to an inner surface of the substrate contact. A system for performing the method includes the semiconductor substrate, a thinning system for thinning the semiconductor substrate, an etching system for forming the substrate opening, and a bonding system for bonding the conductive interconnect to the substrate contact. The semiconductor component can be used to form module components, underfilled components, stacked components, and image sensor semiconductor components.
    Type: Grant
    Filed: May 19, 2005
    Date of Patent: July 1, 2008
    Assignee: Micron Technology, Inc.
    Inventors: Alan G. Wood, William M. Hiatt, David R. Hembree
  • Patent number: 7391117
    Abstract: An interconnect for testing a semiconductor component includes a substrate, and interconnect contacts on the substrate configured to electrically engage component contacts on a semiconductor component. Each interconnect contact includes a compliant conductive layer formed as a conductive spring element. In addition, the complaint conductive layer includes a tip for engaging the component contact and a spring segment portion for resiliently supporting the tip. A method for fabricating the interconnect includes the steps of shaping the substrate, forming a conductive layer on a shaped portion of the substrate and removing at least some of the shaped portion. The shaped portion can comprise a raised step or dome, or a shaped recess in the substrate. The conductive layer can comprise a metal, a conductive polymer or a polymer tape can include a penetrating structure or penetrating particles.
    Type: Grant
    Filed: February 6, 2006
    Date of Patent: June 24, 2008
    Assignee: Micron Technology, Inc.
    Inventors: Kyle K. Kirby, Warren M. Farnworth
  • Patent number: 7388294
    Abstract: A semiconductor package component includes a base die and a secondary die flip chip mounted to the base die. The base die includes a set of stacking contacts for flip chip mounting the secondary die to the base die, and a set of interconnect contacts configured as an internal signal transmission system, and a physical structure for supporting a terminal contact system of the package component. The package component also includes an encapsulant on the base die encapsulating the interconnect contacts, an underfill layer between the dice, and terminal contacts configured for flip chip mounting the package component to a supporting substrate. A method for fabricating the package component includes the steps of providing a base wafer containing a plurality of base dice, and flip chip mounting the secondary dice to the base dice on the base wafer.
    Type: Grant
    Filed: January 27, 2003
    Date of Patent: June 17, 2008
    Assignee: Micron Technology, Inc.
    Inventors: Dean A. Klein, Alan G. Wood, Trung Tri Doan
  • Patent number: 7382060
    Abstract: A semiconductor component includes a thinned semiconductor die having protective polymer layers on up to six surfaces. The component also includes contact bumps on the die embedded in a circuit side polymer layer, and terminal contacts on the contact bumps in a dense area array. A method for fabricating the component includes the steps of providing a substrate containing multiple dice, forming trenches on the substrate proximate to peripheral edges of the dice, and depositing a polymer material into the trenches. In addition, the method includes the steps of planarizing the back side of the substrate to contact the polymer filled trenches, and cutting through the polymer trenches to singulate the components from the substrate. Prior to the singulating step the components can be tested and burned-in while they remain on the substrate.
    Type: Grant
    Filed: February 7, 2005
    Date of Patent: June 3, 2008
    Assignee: Micron Technology, Inc.
    Inventors: Warren M. Farnworth, Alan G. Wood, Trung Tri Doan
  • Patent number: 7371676
    Abstract: A method for fabricating a semiconductor component with a through wire interconnect includes the step of providing a substrate having a circuit side, a back side, and a through via. The method also includes the steps of: threading a wire through the via, forming a contact on the wire on the back side, forming a bonded contact on the wire on the circuit side, and then severing the wire from the bonded contact. The through wire interconnect includes the wire in the via, the contact on the back side and the bonded contact on the circuit side. The contact on the back side, and the bonded contact on the circuit side, permit multiple components to be stacked with electrical connections between adjacent components. A system for performing the method includes the substrate with the via, and a wire bonder having a bonding capillary configured to thread the wire through the via, and form the contact and the bonded contact.
    Type: Grant
    Filed: April 8, 2005
    Date of Patent: May 13, 2008
    Assignee: Micron Technology, Inc.
    Inventor: David R. Hembree
  • Patent number: 7342409
    Abstract: A system for testing semiconductor components includes an interconnect, an alignment system for aligning a substrate to the interconnect, a bonding system for bonding the component to the interconnect, and a heating system for heating the component and the interconnect for separation. The interconnect includes interconnect contacts configured for bonding to, and then separation from component contacts on the components. The system can be utilized with a method that includes the steps of bonding the interconnect to the component to form bonded electrical connections, applying test signals through the bonded electrical connections, and then separating the interconnect from the component. The bonding step can be performed using metallurgical bonding, and the separating step can be performed using solder-wettable and solder non-wettable metal layers on the interconnect or the component.
    Type: Grant
    Filed: September 6, 2006
    Date of Patent: March 11, 2008
    Assignee: Micron Technology, Inc.
    Inventors: Warren M. Farnworth, Mark Tuttle
  • Patent number: 7335978
    Abstract: A semiconductor component includes a stiffener, a circuit decal attached to the stiffener, and a semiconductor die attached to the stiffener. The circuit decal includes conductors which function as an internal signal transmission system for the component, and a mask layer which functions as a solder mask and an outer insulating layer for the component. An adhesive layer in physical contact with the conductors attaches the circuit decal to the stiffener, and electrically insulates the conductors from the stiffener. The component also includes an area array of terminal contacts on the conductors electrically isolated by the mask layer. A method for fabricating the component includes the steps of attaching the circuit decal to the stiffener, attaching the die to the stiffener, interconnecting the die and the circuit decal, encapsulating the die, and forming the terminal contacts.
    Type: Grant
    Filed: May 15, 2006
    Date of Patent: February 26, 2008
    Assignee: Micron Technology, Inc.
    Inventor: Stephen F. Moxham
  • Patent number: 7335994
    Abstract: A semiconductor package component includes a base die and a secondary die flip chip mounted to the base die. The base die includes a set of stacking contacts for flip chip mounting the secondary die to the base die, and a set of interconnect contacts configured as an internal signal transmission system, and a physical structure for supporting a terminal contact system of the package component. The package component also includes an encapsulant on the base die encapsulating the interconnect contacts, an underfill layer between the dice, and terminal contacts configured for flip chip mounting the package component to a supporting substrate. A method for fabricating the package component includes the steps of providing a base wafer containing a plurality of base dice, and flip chip mounting the secondary dice to the base dice on the base wafer.
    Type: Grant
    Filed: June 27, 2005
    Date of Patent: February 26, 2008
    Assignee: Micron Technology, Inc.
    Inventors: Dean A. Klein, Alan G. Wood, Trung Tri Doan
  • Patent number: 7323739
    Abstract: A method for forming a floating gate semiconductor device such as an electrically erasable programmable read only memory is provided. The device includes a silicon substrate having an electrically isolated active area. A gate oxide, as well as other components of a FET (e.g., source, drain) are formed in the active area. A self aligned floating gate is formed by depositing a conductive layer (e.g., polysilicon) into the recess and over the gate oxide. The conductive layer is then chemically mechanically planarized to an endpoint of the isolation layer so that all of the conductive layer except material in the recess and on the gate oxide is removed. Following formation of the floating gate an insulating layer is formed on the floating gate and a control gate is formed on the insulating layer.
    Type: Grant
    Filed: January 13, 2006
    Date of Patent: January 29, 2008
    Assignee: Micron Technology, Inc.
    Inventors: Trung Tri Doan, Tyler A. Lowrey
  • Patent number: 7317322
    Abstract: An interconnect for testing semiconductor components includes a substrate, and contacts on the substrate for making temporary electrical connections with bumped contacts on the components. Each contact includes a recess and a pattern of leads cantilevered over the recess configured to electrically engage a bumped contact. The leads are adapted to move in a z-direction within the recess to accommodate variations in the height and planarity of the bumped contacts. In addition, the leads can include projections for penetrating the bumped contacts, a non-bonding outer layer for preventing bonding to the bumped contacts, and a curved shape which matches a topography of the bumped contacts. The leads can be formed by forming a patterned metal layer on the substrate, by attaching a polymer substrate with the leads thereon to the substrate, or be etching the substrate to form conductive beams.
    Type: Grant
    Filed: October 5, 2005
    Date of Patent: January 8, 2008
    Assignee: Micron Technology, Inc.
    Inventors: Warren M. Farnworth, Salman Akram
  • Patent number: 7314821
    Abstract: An interconnect for testing a semiconductor component includes a substrate, and interconnect contacts on the substrate configured to electrically engage component contacts on a semiconductor component. Each interconnect contact includes a compliant conductive layer formed as a conductive spring element. In addition, the complaint conductive layer includes a tip for engaging the component contact and a spring segment portion for resiliently supporting the tip. A method for fabricating the interconnect includes the steps of shaping the substrate, forming a conductive layer on a shaped portion of the substrate and removing at least some of the shaped portion. The shaped portion can comprise a raised step or dome, or a shaped recess in the substrate. The conductive layer can comprise a metal, a conductive polymer or a polymer tape can include a penetrating structure or penetrating particles.
    Type: Grant
    Filed: January 6, 2005
    Date of Patent: January 1, 2008
    Assignee: Micron Technology, Inc.
    Inventors: Kyle K. Kirby, Warren M. Farnworth
  • Patent number: 7305836
    Abstract: A cryogenic container includes an inner vessel for containing a cryogenic fluid, and an outer vessel for insulating the cryogenic fluid from the environment. The inner vessel includes a superconductive layer formed of a material having superconducting properties at the temperature of the cryogenic fluid. The superconductive layer forms a magnetic field around the cryogenic container, that repels electromagnetic energy, including thermal energy from the environment, keeping the cryogenic fluid at low temperatures. The cryogenic container has a portability and a volume that permits its' use in applications from handheld electronics to vehicles such as alternative fueled vehicles (AFVs). A SMES storage system includes the cryogenic container, and a SMES magnet suspended within the cryogenic fluid. The SMES storage system can also include a recharger and a cryocooler configured to recharge the cryogenic container with the cryogenic fluid.
    Type: Grant
    Filed: May 18, 2005
    Date of Patent: December 11, 2007
    Assignee: Eden Innovations Ltd.
    Inventor: Gregory J. Egan
  • Patent number: 7307348
    Abstract: A semiconductor component includes a semiconductor substrate having a substrate contact, and a through wire interconnect (TWI) bonded to the substrate contact. The through wire interconnect (TWI) includes a via through the substrate contact and the substrate, a wire in the via bonded to the substrate contact, and a contact on the wire. A stacked semiconductor component includes the semiconductor substrate, and a second semiconductor substrate stacked on the substrate and bonded to a through wire interconnect on the substrate. A method for fabricating a semiconductor component with a through wire interconnect includes the steps of providing a semiconductor substrate with a substrate contact, forming a via through the substrate contact and part way through the substrate, placing the wire in the via, bonding the wire to the substrate contact, and then thinning the substrate from a second side to expose a contact on the wire.
    Type: Grant
    Filed: December 7, 2005
    Date of Patent: December 11, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Alan G. Wood, David R. Hembree