Abstract: One embodiment of the present invention provides a system that supports resizing of file system partitions. The system includes one or more storage devices that are divided into a plurality of partitions, wherein each partition includes a different file system. The system operates by receiving a request to allocate storage within a partition. In response to the request, the system adds a request size to a current partition size to produce a predicted size for the partition. Next, the system compares the predicted size for the partition with a size limit for the partition. If the predicted size exceeds the size limit, the system signals an error condition. If the predicted size does not exceed the size limit, the system allocates the requested storage for the partition in the nonvolatile random access memory. The system also makes the current partition size equal to the predicted partition size. In a variation on the above embodiment, the system receives a request to deallocate storage from the partition.

Abstract: A control sequencer circuit issues a sequence of commands to logic devices synchronized to a response by a slave device to a command by a master device. In one instance, the control sequencer circuit is statically adjusted to the timing semantics of the acknowledgment signal of the slave device. The control sequencer circuit includes an event detector, a static sliding window, and a sequencer stage. The event detector receives an acknowledgment signal and a requester ID from a slave device and determines if it is the proper recipient. The static sliding window synchronizes the command sequence to the response by the slave device and adjusts for the timing semantics of the acknowledgment signal of the slave device. The control sequencer stage successively outputs active signals at each clock cycle, thereby generating the command sequence.

Abstract: A method and apparatus used in a storage network facilitates the protection of data in, and replacement of, storage devices about to fail before the failure happens. In a network that includes a set of storage devices organized as a non-redundant (for example RAID 0) array, a storage device about to fail in the non-redundant array can be replaced by another storage device, typically from a pool of spares. The method includes detecting a condition of a first particular storage device in the non-redundant array. Conditions which are detected according to various embodiments indicate that the first particular storage device is suffering events indicating that it is likely to fail, or otherwise suffering from reduced performance. The conditions are detected for example, by the receipt of a signal from the storage device itself, or by the monitoring of statistics concerning the performance of the storage device.

Abstract: A method of designing an integrated circuit, by generating a first netlist for a first router design tool, abstracting the first netlist to mask selected old routes, and generating a second netlist for a second router design tool using new routing information which excludes the masked old routes. In an exemplary use, the first routing tool is an older tool, while the second routing tool is a newer tool that can provide a more compact database and more efficient routing. The first routing tool may use a format (e.g., ASCII) which is different from the format used by the second router design tool (e.g., binary). In such a case, the channel abstraction may involve extracting all channel routes from the first format, and converting the extracted channel routes into the second format. New routes can be established using the second router design tool based on the second netlist, while preserving other old routes.

Abstract: A method of designing an integrated circuit calculates the current density in each metal lead. The method can calculates a mean time to failure for at least one metal lead. The method can assume the metal leads are arranged in series only. The method can calculate the reliability of the integrated circuit. The method can arrange the set of metal leads by reliability. The method can divide the set of metal leads into at least two subsets, a subset requiring redesign and a subset meeting the reliability criteria. An embodiment includes an integrated circuit designed by the method taught. An embodiment includes a computer program product according to the method taught. An embodiment includes an integrated circuit including an integrated circuit designed according to the computer program product.

Abstract: A method and apparatus used in a storage network facilitates the protection of data in, and replacement of, storage devices about to fail before the failure happens. In a network that includes a plurality of sets of storage devices which store respective data sets, a storage device about to fail in one set can be replaced by another storage device from another set of storage devices which is being used to store data having a lower priority. The method comprises assigning priorities to sets of storage devices in the network which store respective data sets. In addition, the method includes detecting a condition of a first particular storage device in a particular set of storage devices that has a first priority. Conditions which are detected according to various embodiments indicate that the first particular storage device is suffering events indicating that it is likely to fail, or otherwise suffering from reduced performance.

Abstract: A system and method are provided for calculating virtual WIP time (“VWIP”) in a multiple-bottleneck, multi-product manufacturing facility. The system and method provide for calculation of one or more bottleneck VWIP values. Each of the bottleneck VWIP values represents the amount of work approaching one of n bottleneck workstations, where n>0. The work approaching the bottleneck workstation comprises at least one of m products, where m>0.

Abstract: A storage server architecture supporting virtual devices and virtual circuits for storing data is provided. The storage server includes a plurality of communication interfaces. A first set of communication interfaces in the plurality is adapted for connection to all kinds of users of data. A second set of communication interfaces in the plurality is adapted for connection to respective devices in a pool of storage devices. Data processing resources in the server are coupled to the plurality of communication interfaces for transferring data among the interfaces. The data processing resources comprise a plurality of driver modules and configurable logic linking driver modules into data paths. Each configured data path acts as a virtual circuit that includes a set of driver modules selected from the plurality of driver modules. A data storage transaction which is received at a communication interface is mapped to one of the configured data paths.

Abstract: A computer system and method modifies operating system files via a self-deleting background process that downloads to a user's desktop and bypasses operating system securities. The background process modifies operating system files including configuration files in a registry via a downloadable desktop component. A method for a computer system having a registry includes installing a background process, bypassing computer operating system securities for the registry via the background process, modifying the registry via the background process, and removing the background process. The method further includes providing a desktop component related to an executable file that executes when the user selects the desktop component. Following the execution of the executable file, the method includes modifying configuration files including registry keys and automatically removing the executable file, the desktop component and files associated with the executable file.

Abstract: A storage server architecture supporting virtual devices and virtual circuits for storing data is provided. The storage server includes a plurality of communication interfaces. A first set of communication interfaces in the plurality is adapted for connection to all kinds of users of data. A second set of communication interfaces in the plurality is adapted for connection to respective devices in a pool of storage devices. Data processing resources in the server are coupled to the plurality of communication interfaces for transferring data among the interfaces. The data processing resources comprise a plurality of driver modules and configurable logic linking driver modules into data paths. Each configured data path acts as a virtual circuit that includes a set of driver modules selected from the plurality of driver modules. A data storage transaction which is received at a communication interface is mapped to one of the configured data paths.

Abstract: A method of designing an integrated circuit calculates the current density in each metal lead. The method can calculates a mean time to failure for at least one metal lead. Calculation of the mean time to failure can include the current density and the temperature. The method can assume the metal leads are arranged in series only. The method can calculate the reliability of the integrated circuit based on temperature effects. The method can arrange the set of metal leads by reliability. The method can divide the set of metal leads into at least two subsets, a subset requiring redesign and a subset meeting the reliability criteria. An embodiment includes an integrated circuit designed by the method taught. An embodiment includes a computer program product according to the method taught. An embodiment includes an integrated circuit including an integrated circuit designed according to the computer program product.

Abstract: The present invention teaches a method for designing an integrated circuit. The design of the integrated circuit is replicated a number of times. The number of times must be odd. The input signals to the original module are also replicated. The replicated modules are configured to respectively receive the replicated input signals. A number of exclusive or gates is provided. The exclusive or gates receive the output signals from the replicated modules. The output signals from the replicated modules are compared to the output signals from the original module. The method is applicable to a bi-directional integrated circuit. Embodiments include the software to replicate the design. Another embodiment includes a computer system for replicating the design. Also, integrated circuits designed by the method described are included within the scope of the disclosure. Another embodiment includes designs produced by the method.

Abstract: A method and system for use in wafer fabrication quality control. The method and system make quantitative a qualitative integrated circuit wafer defect signature. In response to the quantitativize wafer fabrication defect signature, the method and system identify at least one cause of the defect signature.

Abstract: Minimization of waste of information processing resources by orphan computer processes in an information processing system is provided by: assembling information regarding active computer processes on a computer system; classifying each of the active computer processes for which information was assembled as one of a group consisting of legitimate computer processes and orphan computer processes; and processing the orphan computer processes according to an orphan processing protocol.

Abstract: The present invention provides a method for centralized and managed loading of boot images into one or more processors that are part of a file server for a mass storage system. In a computer system having at least one first controller, at least one input output processor (IOP), a first bus and a second bus, the present invention includes the steps of detecting readiness of the IOP to load a boot image, identifying across the first bus a location where the boot image will be loaded and loading the boot image across the second bus. The first controller may determine which of a plurality of boot images should be loaded. The first controller and the IOP may each have first and second processors, with communication between the first processors being across the first bus and boot images being accessed by the second processors across the second bus.

Abstract: A memory system with non-volatile integrated circuit memory devices including an interface for a high speed bus is described, supporting continuous writes at the bus speed, without the possibility of buffer overrun during most conditions. The system comprises an memory bus, an system buffer, an array of non-volatile storage units, such as flash memory devices, and an interconnect system supporting data transfer among the components. The array includes sets and subsets of non-volatile storage units, referred to herein for convenience as platters having multiple banks, banks having multiple columns, and columns having multiple storage units. The storage units comprises integrated circuit memory having page buffers, with input ports. In one example, the array includes two platters, eight banks per platter, four columns per bank, and eight storage units per column, for a total of 256 storage units. The system buffer includes at least the same number of stores as columns in each bank.

Abstract: An electronic circuit has a register connected to a sense amplifier via a bitline (the sense amplifier has a primary precharge circuit), and a secondary precharge circuit also connected to the bitline. For bitlines that are relatively long, the secondary precharge circuit is located at a distal end of the bitline with respect to the sense amplifier. The secondary precharge circuit initially pulls up the voltage of the bitline, and the primary precharge circuit in the sense amplifier completes the precharging of the bitline. The secondary precharge circuit includes a cascode transistor coupled to the bitline via a feedback circuit. The feedback circuit is enabled during the precharge phase, when the bitline is discharged below a preset threshold. The threshold of the secondary precharge circuit can be set such that any skew between the precharge pulses of the secondary precharge circuit and the sense amplifier does not affect the falling bitline during the sense amplifier evaluate phase.

Abstract: A storage server comprising: a processing unit, a bus system coupled with the processing unit, including a plurality of slots, slots in the plurality of slots including interfaces to respective data stores; a communication interface; and an operating system coupled with the processing unit the operating system including: logic controlling transfers among the plurality of slots over the bus system according to an internal format, logic for translating a storage transaction received over the communication interface into the internal format, and logic for configuring the plurality of slots according to a configuration data.

Abstract: A speech recognition system utilizes multiple quantizers to process frequency parameters and mean compensated frequency parameters derived from an input signal. The quantizers may be matrix and vector quantizer pairs, and such quantizer pairs may also function as front ends to a second stage speech classifiers such as hidden Markov models (HMMs) and/or utilizes neural network postprocessing to, for example, improve speech recognition performance. Mean compensating the frequency parameters can remove noise frequency components that remain approximately constant during the duration of the input signal. HMM initial state and state transition probabilities derived from common quantizer types and the same input signal may be consolidated to improve recognition system performance and efficiency. Matrix quantization exploits the “evolution” of the speech short-term spectral envelopes as well as frequency domain information, and vector quantization (VQ) primarily operates on frequency domain information.

Abstract: A card management system architecture for managed startup of a system and for monitoring its operation is provided. Both a method and device particularly suited to carrying out the method are provided. According to one embodiment of the method, a second controller evaluates the status of power supplies and then powers up a first controller and processors on input-output processors (IOPs). The first controller evaluates the status of individual IOPs and enables additional power and data interfaces. Additional embodiments involve additional structures and steps. Redundant channels for communications among controllers and IOPs are preferred. In one embodiment, the first bus is implemented as five serial communication lines. Communication between redundant first controllers and between redundant second controllers allows determination of which controllers should be active.