Abstract: There is described a method, system and computer program product for processing a link embedded in a link document in a client computer, said link comprises a URL reference for a URL document in the client computer or another computer, there being stored a record containing a link reference and an intended fingerprint, said intended fingerprint representing the content of the URL document associated with the URL of the link at the time of or after the link was created, said method comprising the steps of: fetching the intended fingerprint for the link; fetching the URL document; creating a current fingerprint of the fetched URL document; comparing the intended fingerprint and the current fingerprint; and identifying that the intended fingerprint and the current fingerprint are different in a material way.

Abstract: A mechanism is provided, in a data processing system, for accessing memory based on an effective address submitted by a process of a partition. The mechanism may translate the effective address into a virtual address using a segment look-aside buffer. The mechanism may further translate the virtual address into a partition real address using a page table. Moreover, the mechanism may translate the partition real address into a system real address using a logical partition real memory map for the partition. The system real address may then be used to access the memory.

Abstract: An access speculation predictor is provided that may be implemented using idle command processing resources, such as registers of idle finite state machines (FSMs) in a memory controller. The access speculation predictor may predict whether to perform speculative retrieval of data for a data request from a main memory of the data processing system based on history information stored for a memory region targeted by the data request. In particular, a first address may be extracted from the data request and compared to memory regions associated with second addresses stored in address registers of a plurality of FSMs of the memory controller. A FSM whose memory region includes the first address may be selected. History information for the memory region may be obtained from the selected FSM. The history information may be used to control whether to speculatively retrieve the data for the data request from a main memory.

Abstract: Mechanisms, in a data processing system, are provided for tracking effective addresses through a processor pipeline of the data processing system. The mechanisms comprise logic for fetching an instruction from an instruction cache and associating, by an effective address table logic in the data processing system, an entry in an effective address table (EAT) data structure with the fetched instruction. The mechanisms further comprise logic for associating an effective address tag (eatag) with the fetched instruction, the eatag comprising a base eatag that points to the entry in the EAT and an eatag offset. Moreover, the mechanisms comprise logic for processing the instruction through the processor pipeline by processing the eatag.

Abstract: An access speculation predictor may predict whether to perform speculative retrieval of data for a data request from a main memory based on whether or not a domain indicator in the data request indicates that the cache line corresponding to the data has a special invalid state or not. In particular, a first address and a domain indicator are extracted from first data request. The first address is used to select a finite state machine (FSM) of a memory controller based on memory regions associated with the FSMs of the memory controller. Speculative retrieval of data for the first data request from main memory is controlled based on whether the domain indicator identifies the special invalid state or not and, if the domain indicator identifies that the cache line does not have the special invalid state, based on information stored in registers associated with the selected FSM.

Abstract: Mechanisms for providing hardware based dynamic load balancing of message passing interface (MPI) tasks are provided. Mechanisms for adjusting the balance of processing workloads of the processors executing tasks of an MPI job are provided so as to minimize wait periods for waiting for all of the processors to call a synchronization operation. Each processor has an associated hardware implemented MPI load balancing controller. The MPI load balancing controller maintains a history that provides a profile of the tasks with regard to their calls to synchronization operations. From this information, it can be determined which processors should have their processing loads lightened and which processors are able to handle additional processing loads without significantly negatively affecting the overall operation of the parallel execution system. As a result, operations may be performed to shift workloads from the slowest processor to one or more of the faster processors.

Abstract: An access speculation predictor may predict whether to perform speculative retrieval of data for a data request from a main memory based on whether or not a current requestor tag matches a previous requestor tag. In particular, a first address and a first requester tag may be extracted from a first data request and a finite state machine (FSM) of a memory controller may be selected whose memory region includes the first address. A second requester tag, that identifies a previous requester that attempted to access the memory region association with the selected FSM, may be retrieved from a register associated with the selected FSM and compared to the first requester tag. Speculatively retrieving the data for the first data request from a main memory may be controlled based on results of the comparison of the first requester tag to the second requester tag.

Abstract: An access speculation predictor may predict whether to perform speculative retrieval of data for a data request from a main memory based on whether a scope predictor indicates whether a local or global request is predicted to be necessary to obtain the data for the data request. In particular, a first address and a scope predictor may be extracted from a first data request. A determination may be made as to whether a memory controller receiving the first data request is local to a source of the first data request or not. Speculative retrieval of the data for the first data request from a main memory may be controlled based on whether the memory controller is local to the source of the first data request and whether the scope predictor identifies whether a local or a global request is predicted to be necessary.

Abstract: Mechanisms of memory management in a scoped memory system of a data processing system having a one or more scoped memory areas are provided. The mechanisms identify a set of one or more child scoped memory areas of the scoped memory area for garbage collection. The mechanisms further identify, in each scoped memory area of the set, references to the scoped memory area for garbage collection as root references for objects allocated in the scoped memory area of the scoped memory system, thereby generating a set of root references. The mechanisms also recursively traversing and marking objects that are referenced from the set of root references and that are allocated in the scoped memory area of the scoped memory system and identify objects in the scoped memory area of the scoped memory system that are not so marked. The identified objects are discarded from the scoped memory system.

Abstract: The shared memory includes a header section and a data section, wherein said header section includes at least two headers in which control information is stored. The method comprises the steps of: judging whether or not there is data corruption in one of said at least two headers; and copying the control information in any one of other headers to said one header if there is data corruption in said one header. A method for controlling access to a shared memory is also disclosed.

Abstract: Providing access to a shared resource in a computing environment involves maintaining a timestamp for each shared resource, the timestamp representing the time the resource was last accessed. Then, detecting if the resource is reserved before obtaining access to the resource, by reading the resource timestamp, and if the timestamp represents a future time relative to the current time, indicating that the resource is reserved and delaying access to the resource. If the resource is unreserved, then accessing the resource by reading the resource timestamp to detect any changes in the timestamp since the last reading; if unchanged, then accessing the resource. If the resource is unreserved, then obtaining exclusive access to the resource by reserving the resource by incrementing its timestamp by a reservation period; accessing the resource; and resetting the resource timestamp to the current time.

Abstract: Mechanisms for modifying an operation of one or more processors executing message passing interface (MPI) tasks are provided. Mechanisms for adjusting the balance of processing work loads of the processors are provided so as to minimize wait periods for waiting for all of the processors to call a synchronization operation. Each processor has an associated hardware implemented MPI load balancing controller. The MPI Load balancing controller maintains a history that provides a profile of the tasks with regard to their calls to synchronization operations. From this information, it can be determined which processors should have their processing loads lightened and which processors are able to handle additional processing loads without significantly negatively affecting the overall operation of the parallel execution system. As a result, operations may be performed to shift workloads from the slowest processor to one or more of the faster processors.

Abstract: Mechanisms for providing an encrypted file system are provided. The mechanisms use a combination of encryption methodologies so as to reduce the amount of decryption and re-encryption that is necessary to a file in the Encrypted File System in the event that the file needs to be modified. The encryption methodologies are interleaved, or alternated, with regard to each block of plaintext. In one illustrative embodiment, Plaintext Block Chaining (PBC) and Cipher Block Chaining (CBC) encryption methodologies are alternated for encrypting a sequence of blocks of data. The encryption of a block of plaintext is dependent upon the plaintext or a cipher generated for the plaintext of a previous block of data in the sequence of blocks of data so that the encryption is more secure than known Electronic Code Book encryption methodologies.

Abstract: A design structure for a circuit for obtaining a desired phase locked loop (PLL) duty cycle without a pre-scaler is provided. The PLL circuit of the illustrative embodiments utilizes two separate loops that simultaneously operate on the VCO. One loop ensures the frequency and phase lock while the other loop ensures the duty cycle lock. The VCO is modified to have an additional control port to adjust the duty cycle. Thus, the VCO has one control port for performing frequency adjustment and one control port for duty cycle adjustment. As a result, both the duty cycle and the frequency may be controlled using the VCO of the PLL circuit of the illustrative embodiments so as to achieve any desired duty cycle output without requiring a VCO pre-scaler circuit or duty cycle correction circuit.

Abstract: Systems, methods and media for database synchronization on a network are disclosed. More particularly, hardware and/or software for database synchronization on a network protected with firewalls are disclosed. Embodiments include an e-mail listener for receiving e-mails from a plurality of computer systems and modifying a central database based on the received e-mails. In one embodiment, the computers systems and central database are protected by a firewall. Other embodiments provide for a transaction log that includes information about received e-mails. In these embodiments, the transaction log may optionally be used to synchronize other databases, including local databases located at the computer systems.

Abstract: Mechanisms for enabling both native and non-native input/output virtualization (IOV) in a single I/O adapter are provided. The mechanisms allow a system with a large number of logical partitions (LPARs) and system images to use IOV to share a native IOV enabled I/O adapter or endpoint that does not implement the necessary number of virtual functions (VFs) for each LPAR and system image. A number of VFs supported by the I/O adapter, less one, are assigned to LPARs and system images so that they may make use of native IOV using these VFs. The remaining VF is associated with a virtual intermediary (VI) which handles non-native IOV of the I/O adapter. Any remaining LPARs and system images share the I/O adapter using the non-native IOV via the VI. Thus, any number of LPARs and system images may share the same I/O adapter or endpoint.

Abstract: A system and method for multi-level security filtering of model representations. Elements of an architecture and systems engineering model have associated security characteristics identifying the required level of security that a user must have in order to be able to obtain access to information about that element of the model. Based on these security characteristics and the security level of a user attempting to access the model, the content of the model is modified such that elements that are not accessible by a user having that security level are obscured or not visible to the user. The other elements of the model which are accessible by the user based on his/her security level are modified in the modified model so as to not provide information that would disclose the nature, character, or in some cases even the presence, of the elements that are not accessible by the user based on his/her security level.

Abstract: Mechanisms for securing dynamic discovery of an enterprise computing infrastructure is provided. One implementation involves maintaining enterprise credential information in a secured trust store, receiving an access request through a secure connection for access to a remote infrastructure component, determining the type of the access request, for a root-level type access request, responding to the request via the secure connection with enterprise root credentials from the trust store, and for an unprivileged type access request, responding to the request via the secure connection with unprivileged access enterprise credentials from the trust store.

Abstract: Methods, apparatus, and products for staging a file within a distributed computing system are disclosed that include defining a topology of the network; mapping each computer to a network location in the topology of the network; selecting, in dependence upon the topology of the network and the network locations of the computers in the network, one or more servers on which to stage the file for use by clients in the network; and staging the file on the one or more selected servers. The distributed computing system includes a plurality of computers coupled for data communications through a data communications network, the distributed computing system also includes files of computer data and computer program instructions for use by the computers, the computers include clients that use the files and servers capable of functioning as staging locations for files for use by the computers in the network.

Abstract: Mechanisms are disclosed for adjusting a fast re-transmit threshold (FRT) value for transmitting data streams over a computer system. One embodiment includes receiving, by a sender, a current fast re-transmit threshold value for a packet from a receiver. Further, these mechanisms include decreasing the size of the congestion window of the sender, and re-transmitting the packet to the receiver in network communication with the sender. Further still, the mechanisms include counting, by the sender, a number of dupacks after re-transmitting the packet until arrival, at the sender, of an acknowledgement (ACK) for the packet. Yet further, the mechanisms include determining, based on the size of the congestion window and the counting, a value of the FRT value. If the sender receives the ACK for the packet in less than one round trip time, then this may be a re-ordering problem for re-setting the FRT value.