Abstract: A method and system are disclosed for limiting the processing power of a CPU or CPUs in a multi-processing system comprising at least one constrained or hobbled CPU and a main memory. The novel method includes executing a high priority process on the CPU which effectively interrupts the processing of a task at a predetermined time T.sub.1 during a full time cycle T.sub.0 -T.sub.2 rendering the CPU unavailable for a predetermined period of time (T.sub.1 to T.sub.2) which represents a predetermined percentage of the CPUs full computing power. The task that is interrupted is continued at the start of the next time cycle of the CPU so that all tasks are completed. The power of any CPU so hobbled may be decreased by a predetermined percentage of full power by decreasing the processing time cycle between T.sub.0 and T.sub.1, without the need for hardware or operating system modification.

Abstract: A method and apparatus enables a newly installed peripheral device such as a disk device to be used with a computer system without changing the operating system. The peripheral device is identified as a type which is not recognized by an operating system operating in conjunction with the computer system. A value which identifies at least one logical attribute of said peripheral device is obtained from said peripheral device. A determination is made as to whether the operating system and the peripheral device are compatible based on the logical attribute obtained from the peripheral device. The operating system and the peripheral device communicate if it is determined that the operating system and the peripheral device are compatible (i.e., can operate together).

Abstract: In a spread spectrum multipoint-to-point communication system there is provided a novel frequency to phase converter, for automatically synchronizing the PN codes of the user transmitters/receiver with the receiver/transmitter in the central hub. The highly accurate frequency to phase converter generates a highly accurate phase error signal for synchronizing the multiuser network. The frequency to phase converter includes a serial adder and a series to parallel converter and a shift register which integrates the highly accurate phase error signal values and produces a highly accurate frequency value which is applied to the input of the resident processor in the central hub transmitter/receiver. The central hub transmitter/receiver calculates the clock offset for synchronizing each of the user receiver transmitters and generates a clock adjusting signal which is transmitted to the user receiver/transmitters.