Abstract: An electronic circuit verification system and method includes an HDL circuit simulator and a circuit simulation verifier that pass control back and forth between each other, and that cooperate so as to perform circuit verification tasks than would be very difficult to perform using only the HDL circuit simulator. The circuit simulation verifier executes a test bench so as to define operational correctness and/or performance criteria, including at least one Expect Event, each Expect Event comprising a combination of one or more signal values that are expected to occur during simulation, and a time frame during which the signal value combination is expected to occur. The circuit simulation verifier includes instructions for blocking execution of a thread of execution associated with the test bench until the earlier of the combination of one or more signal values occurring during simulation and the time frame expiring.

Abstract: A memory system is able to simultaneously access multiple rows in page mode operation. The multiple page memory includes a memory array with multiple internal read registers to improve the effective page cycle time. The multiple page memory of this invention is very effective in graphics applications where multiple page memory access is required. A memory with multiple page random access in accordance with this invention greatly enhances performance by allowing different sources to continue to access the memory in the page mode, in spite of intervening memory accesses by other sources to other rows of the memory. A VRAM with multiple page random access in accordance with this invention provides an even higher performance graphic memory system.

Abstract: The present invention simulates the effect of non-homogenous fog in computer graphics images. The non-homogenous fog visibility equation includes four parameters. A distance scaling parameter K1. A variable fog parameter K2. A normalization constant K3, and a scaling constant K4. The visibility at a sample point can be determined using the visibility equation: ##EQU1## where Z.sub.ns is a normalized and scaled image distance which is equal to (K4*K1*Z)+(K4*K2). To improve computational efficiency the visibility function can be evaluated using a lookup table. The lookup table of the present invention has an efficient addressing scheme and a minimum number of output steps. The visibility function can be expressed as a function of a fog ratio and a fog distance. The fog distance is a distance from the viewpoint to the point where the visibility is reduced to 37% of full visibility. The fog ratio is the square root of the ratio of "near fog" density to "far fog" density.

Abstract: A novel method is taught to quickly and easily produce assember code from a single embedded file which can include high level language code written in any of a number of high level languages interspersed, if desired, among assembler code itself.

Abstract: The present invention pertains to a method for determining if data read from a storage medium has been read from physical block address (PBA) other than the expected PBA. Data that is stored on the data storage medium is encoded in accordance with a protocol that includes randomizing the data and combining the first k.times.2t bytes of the data with a PBA string, where t is the error correction capacity associated with the error correction technique used in the data storage system and k is the number of bytes of the PBA that are used in the PBA string. In addition, the data is k-way interleaved with parity data appended to it. When the data is read from the data storage medium, the data is decoded using a scheme corresponding to the encoding protocol. If errors are present in the data and exceed the error correction capacity, the first 2t bytes of each interleave are marked as erasures and a second correction is performed by an error correction unit.

Abstract: A multiple chip self-aligning clock distribution system. The clock signal provided to any given chip is delayed by the on-chip distribution time of every other chip with which it is to be synchronized. Equal delay paths are added to each chip which provide a delay equal to the clock distribution delay of the chip. The equal delay paths can comprise a series of logic gates, such as for example inverters. The clock distribution delay of the equal delay path is designed to be equal to the clock distribution delay of the clock distribution tree on the chip. For each chip to be synchronized, the clock signal is routed through an equal delay path on each of the other chips to be synchronized before being coupled to the clock distribution input terminal of the destination chip. The number of equal delay paths that is included on each chip is a function of the number of chips to be synchronized. "N" equal delay paths are used where the number of chips is greater than 2.sup.N-1 and is less than or equal to 2.sup.N.

Abstract: A memory system is able to simultaneously access multiple rows in page mode operation. The multiple page memory includes a memory array with multiple internal read registers to improve the effective page cycle time. The multiple page memory of this invention is very effective in graphics applications where multiple page memory access is required. A memory with multiple page random access in accordance with this invention greatly enhances performance by allowing different sources to continue to access the memory in the page mode, in spite of intervening memory accesses by other sources to other rows of the memory. A VRAM with multiple page random access in accordance with this invention provides an even higher performance graphic memory system.

Abstract: A novel method and apparatus for decoding a compressed audio/video signal to produce decoded audio and decoded video signals. The decoding tasks are partitioned into "pre-processing tasks" and "post-processing tasks." Pre-processing tasks involve one or more non-signal processing oriented operations which do not require extensive computing resources. Pre-processing tasks are assigned to be executed by the host processor, which can perform these tasks without straining it computational resources. Pre-processing tasks include demultiplexing the compressed audio/video stream into compressed audio and compressed video streams, performing audio pre-processing on the compressed audio stream and performing video pre-processing on the compressed video stream. Post-processing tasks involve one or more signal processing oriented operations which require extensive computing resources. Pre-processing tasks are assigned to be executed by a dedicated subprocessor.

Abstract: A novel apparatus and method is disclosed to decode an encoded MPEG video stream in an efficient manner making optimal use of available system memory and computational resources. The present invention partitions the MPEG video decode task into software tasks which are executed by a CPU and hardware tasks which are implemented in dedicated video hardware. Software tasks represent those tasks which do not require extensive memory or computational resources. On the other hand, tasks implemented in dedicated video hardware represent those tasks which involve computational and memory mintensive operations. Synchronization between software tasks executed by the CPU and hardware tasks implemented in dedicated video hardware is achieved by means of various data structures, control structures and device drivers.

Abstract: A novel apparatus and method is disclosed to perform discrete cosine transform (DCT) coefficient reconstruction more efficiently and using less hardware resources than prior art techniques. The invention comprises a correction factor generator apparatus which computes a correction factor which is used in the DCT coefficient reconstruction process. Use of the correction factor enables DCT coefficient reconstruction to be performed using lesser computations and lesser hardware resources than prior art techniques. The apparatus and method can be used to perform DCT coefficient reconstruction for both MPEG-1 and MPEG-2 encoded video data streams.

Abstract: A novel apparatus and method is disclosed to assure validity of data accessed from synchronous memory during a "read" operation, wherein the synchronous memory is operating synchronously at a high frequency system clock. The invention comprises a programmable delay module which generates a skewed clock signal which is used to clock in data read from the synchronous memory. The programmable delay module generates the skewed clock signal by adding programmable time delays to the system clock signal. The inserted delay increases the data valid window time available for the "read" operation and allows sufficient setup and hold time for valid data to be read by a memory controller.

Abstract: A novel memory structure in which memory arrays are organized in sectors with each sector being formed of a single column or a group of columns having their control gates connected in common. In one embodiment, a high speed shift register is used in place of a row decoder to serially shift in data for the word lines, with all data for each word line of a sector being contained in the shift register on completion of its serial loading. In one embodiment, speed is improved by utilizing a parallel loaded buffer register which receives parallel data from the high speed shift register and holds that data during the write operation, allowing the shift register to receive serial loaded data during the write operation for use in a subsequent write operation.

Abstract: A video server is taught which is capable of outputting a plurality of video streams simultaneously. Each video stream is synchronized at two levels of synchronization: coarse-grain and fine-grain. The coarse-grain synchronization is carried out in software over a plurality of packets of data, and the fine-grain synchronization carried out using the network clock. By utilizing both coarse-grain and fine-grain synchronization as taught by this invention, drift and jitter are controlled, providing accurate presentation of constant bit rate data to a receiving device. As another feature of this invention, a bit pump is utilized which includes header information such as constant bit rate information, and information regarding the rates associated with the coarse-grain and fine-grain synchronization. By utilizing this preinitialized header information, CPU demands are reduced as compared with prior art systems in which the CPU must look up timing information from the data to be transmitted.

Abstract: Novel memory cells utilize source-side injection, allowing very small programming currents. If desired, to-be-programmed cells are programmed simultaneously while not requiring an unacceptably large programming current for any given programming operation. In one embodiment, memory arrays are organized in sectors with each sector being formed of a single column or a group of columns having their control gates connected in common. In one embodiment, a high speed shift register is used in place of a row decoder to serially shift in data for the word lines, with all data for each word line of a sector being contained in the shift register on completion of its serial loading. In one embodiment, speed is improved by utilizing a parallel loaded buffer register which receives parallel data from the high speed shift register and holds that data during the write operation, allowing the shift register to receive serial loaded data during the write operation for use in a subsequent write operation.

Abstract: A memory system is able to simultaneously access multiple rows in page mode operation. The multiple page memory includes a memory array with multiple internal read registers to improve the effective page cycle time. The multiple page memory of this invention is very effective in graphics applications where multiple page memory access is required. A memory with multiple page random access in accordance with this invention greatly enhances performance by allowing different sources to continue to access the memory in the page mode, in spite of intervening memory accesses by other sources to other rows of the memory. A VRAM with multiple page random access in accordance with this invention provides an even higher performance graphic memory system.

Abstract: The fabrication of thin film inductors on a substrate, which may include thin film resistors, thin film capacitors, and semiconductor devices. In one embodiment an inductor is fabricated initially on a substrate and then integrated with other devices subsequently formed on the substrate. In this embodiment, process steps used to fabricate such other devices utilize temperatures sufficiently low to prevent damaging or destroying the characteristics of the inductor. In another embodiment the fabrication of an inductor is achieved through photoresist masking and plating techniques. In alternative embodiments, fabrication of an inductor is achieved by sputtering, photoresist processes and etching/ion-milling techniques. A combination of various individual process steps from various embodiments are suitable for use to fabricate the individual layers to achieve a structure of this invention.

Abstract: P channel EEPROM cells are designed for integration into arrays written with single polarity signals developed from small, low power charge pumps. These cells reduce the additional masking steps that must be added to a CMOS logic process for EEPROM to only one additional step. The novel cells of this invention enable the array to function with a V.sub.PP about 2 V less than that required by an N channel EEPROM cell, with similar writing speed and tunnel oxide thickness.

Abstract: A novel method and structure for the implementation of Half Pixel Filtering and Block Averaging that are efficient for implementation on a general purpose CPU. The number of required operations are reduced by operating on multiple pixels simultaneously using sliced arithmetic, while maintaining full accuracy. In certain embodiments, the number of operations are further reduced by compromising full accuracy. This approximation is applicable to decoding of bi-directional frames.

Abstract: A system and method is capable of providing a much more effective enterprise-wide decision support system. It consists of an integrated end-to-end solution including automatic generation of data warehouses or data marts integrated with automatic delivery of information from the data warehouses or data marts to knowledge workers throughout the enterprise using a "publish and subscribe" paradigm for dissemination of the information at any time, to any places, in any formats to any number of knowledge workers. This integration allows information in the data warehouses or data marts to be delivered immediately after every refresh of the data warehouses or data marts thereby allowing maximum utilization of the valuable information in the data warehouses or data marts throughout the enterprise to gain the most optimum decision support.

Abstract: In accordance with the teachings of this invention, a novel voltage regulator is taught which is capable of being formed solely of MOS devices. This eliminates the need to utilize off chip components to form a stand-alone voltage regulator, and avoid the process complexities and increased cost associated with BICMOS fabrication processes.