Abstract: Disclosed is a complementary vertical NPN and PNP pair having matched performance. The PNP collector is located deep in an epitaxial layer overlying a semiconductor substrate. The junction depths and surface concentrations of both emitters are quite similar; the junction depths and surface concentrations of bases of the complementary devices are also similar to each other. The PNP and NPN emitters are provided with self-aligned conductive contacts. A high dopant concentration equal to that in the emitters is provided in all contacts of the transistor elements to reduce the contact resistances.Disclosed too is a process of forming the above structure. Starting with a semiconductor substrate having a blanket N+ NPN subcollector and an epitaxial layer thereon having first and second active regions, an NPN base precursor and PNP collector reach-through precursor are simultaneously implanted in the first and second active regions, respectively.

Abstract: Disclosed is a process for forming self-aligned low resistance ohmic contact to a P doped region (e.g., base of an NPN device) in conjunction with forming similar contact to a (highly) N doped region (e.g., emitter of NPN). After forming a P doped region in an N type monocrystalline silicon body and masking it with an insulator (e.g. dual oxide-nitride) layer, the highly doped N region (hereafter, N+ region) is formed in a portion of the P doped region by selectively opening the insulator layer and introducing N dopant therethrough. This opening also serves as contact opening for the N+ region. contact opening for the P region is formed by selectively etching the insulator layer. The structure is subjected to a low temperature steam oxidation to from an oxide layers in the P contact and N+ contact regions, the oxide in the N+ contact being about 3-5 times thicker than that in the P contact region due to the significantly higher oxidation rate of the N+ region relative to the P doped region.

Abstract: A method and resulting structure for making contact to a narrow width PN junction region in any desired semiconductor body is described. A substantially vertical conformal conductive layer is formed over the desired PN junction region. The body is heated at a suitable temperature to cause a dopant to diffuse from the vertical conductive layer into the semiconductor body to form the narrow width PN junction region. A substantially horizontal conductive layer makes contact to the substantially vertical layer so as to have the horizontal conductive layer in electrical contact to the PN junction region. Electrical contact can be made to the horizontal conductive layer at any convenient location. A lateral PNP transistor is one type of very small device that can be made using the method of the present invention.

Abstract: Disclosed is a process for reducing lithographic image size for integrated circuit manufacture. A mask of photosensitive material having an opening of a minimum size dictated by the limits of lithography is formed on a substrate. Reduction in the image size is achieved by establishing sidewalls to the interior vertical surfaces of the opening by depositing a conformal layer, followed by anisotropic etching. The dimension of the opening is reduced by the combined thickness of the two opposite insulator sidewalls.In a specific direct application of the disclosed process, a photomask/stencil having a pattern of openings of a minimum size smaller than possible by lithography, per se, is formed.

Abstract: A high density integrated circuit structure, for example a dynamic memory cell, is described which includes an active/passive device in combination with a capacitor structure. The capacitor structure is of the polysilicon-oxide-silicon type and is formed on the sidewalls of a mesa-shaped and dielectrically isolated region of silicon material resulting from the formation of an isolation trench in the silicon. The trench is filled with a plastic material, such as polyimide. The capacitor is formed by the isolated region of silicon material which functions as the first capacitor plate, a doped polysilicon layer provided on the vertical walls of the mesa serving as the second capacitor plate and a thin dielectric layer interposed between the two plates serving as the capacitor's dielectric. Since the polysilicon is wrapped around the periphery of the mesa as a coating on the vertical sidewalls thereof, it gives rise to a large storage capacitance without an increase in the cell size.

Abstract: A method is disclosed for fabricating a small area, self aligned guard ring in a Schottky barrier diode. A vertically-walled hole is anisotropically etched completely through a dielectric layer on a silicon substrate. A layer of doped polycrystalline silicon is deposited over the apertured dielectric layer. The polycrystalline silicon is reactively ion etched away to leave only a lining about the perimeter of the hole in the dielectric layer. The structure is heated to diffuse the dopant from the lining into the substrate. Schottky diode metal is deposited on the substrate exposed through the lined aperture in the dielectric layer.

Abstract: Disclosed is a process for forming a high-speed, self-aligned GaAs-gate field effect transistor with submicron channel length. Starting with a semi-insulating GaAs substrate having a thin gate insulator layer of undoped AlGaAs and a comparatively thick highly doped GaAs layer, a metal contacting the doped GaAs layer is controllably formed by sidewall image transfer and planarization etchback technique. The thickness and width of the metal strip are in the low submicron range. Using the metal strip as a mask, the doped GaAs is patterned into a GaAs gate for the FET having the characteristics of submicron width (i.e., the dimension of the gate measured along the source-drain), substantially vertical walls and contacted on the top thereof in a self-aligned relationship by the metal strip. Next, a submicron wide insulator sidewall is formed on the vertical walls of the gate.

Abstract: Disclosed is a process of forming high density, planar, single- or multi-level wiring for a semiconductor integrated circuit chip. On the chip surface is provided a dual layer of an insulator and hardened photoresist having various sized openings (grooves for wiring and openings for contacts) therein in a pattern of the desired wiring. A conductive (e.g., metal) layer of a thickness equal to that of the insulator is deposited filling the grooves and contact openings. A sacrificial dual (lower and upper component) layer of (hardened) photoresist is formed filling the metal valleys and obtaining a substantially planar surface. The lower component layer is thin and conformal and has a higher etch rate than the upper component layer which is thick and nonconformal. By reactive ion etching the sacrificial layer is removed leaving resist plugs in the metal valleys.

Abstract: Submicron lateral device structures, such as bipolar transistors, Schottky Barrier diodes and resistors, are made using self-aligned fabrication techniques and conventional photolithography. The devices are made using individual submicron silicon protrusions which extend outwardly from and are integral with a silicon pedestal therefor. Both PNP and NPN transistors may be made by diffusing approximate dopant materials into opposing vertical walls of a protrusion so as to form the emitter and collector regions. The protrusions themselves are formed by anisotropically etching the silicon using submicron insulating studs as a mask. The studs are formed using sidewall technology where a vertical sidewall section of a layer of insulating material is residual to a reactive ion etching process employed to remove the layer of insulating material.

Abstract: The present invention provides an improved etchant composition and method for the resistivity specific etching of doped silicon films which overlie intrinsic or lightly doped crystal regions. The composition of the etchant is 0.2-6 mole % hydrofluoric acid, 14-28 mole % nitric acid, and 66-86 mole % acetic acid/water. The etchant leaves no silicon residue and provides for controlled etching with an etch stop at the lightly doped or intrinsic region.

Abstract: Disclosed is a nondestructive optical method for detecting defects (e.g., open regions) in thin opaque or non-opaque films formed on a ceramic substrate by utilizing the inherent fluoresceability of the ceramic material. The film-clad ceramic is illuminated with an intense optical radiation consisting of at least one wavelength which corresponds to the excitation band(s) of the ceramic component responsible for fluorescence. In case of an opaque film, the incident light will reach the ceramic in regions corresponding to the defects causing these ceramic regions to fluoresce at a different wavelength than that of the incident light. The fluorescent radiation emanating from the ceramic will provide a high contrast optical image of the defects particularly when viewed through a filter which transmits only the fluorescent radiation. In case the film is non-opaque, the incident light will generate fluorescent radiation over the entire substrate--both the defective and non-defective regions.

Abstract: Sintering of metal particles at their normal sintering temperature is inhibited by coating the metal particles with an organic material such as polyvinyl butyral, polyvinyl formvar, polyvinyl alcohol, polyacrylonitrile epoxies, urethanes and cross-linked polyvinyl butyral. The organic coating serves as a barrier preventing physical contact between metal particles during the initial phase of the sintering cycle and degrades into a carbonaceous coating followed by volatilization during the intermediate phase of the cycle permitting coalescence of the metal particles into a dense mass along with the coalescence of the glass-ceramic particles. Co-sintering of the metal particles and the glass-ceramic particles with the aid of the organic coating results in a hermetic multi-layer glass ceramic substrate free of dimensional stability problems without deleteriously affecting the electrical conductivity of the metal conductor pattern.

Abstract: Disclosed is a process of growing a conformal and etch-resistant silicon dioxide on a surface by forming a conformal layer of polysilicon and subjecting the polysilicon to thermal oxidation to completely convert the polysilicon into (poly) silicon oxide.Disclosed also is a method of forming an isolation trench in a semiconductor substrate having a high integrity oxide sidewall. After forming the trench in the substrate surface using a suitable etch mask and RIE, a single (thermal) oxide or dual (thermal) oxide and (CVD) nitride liner is formed on all trench surfaces. A conformal layer of undoped polysilicon is then formed (by. e.g. LPCVD) on the liner. By subjecting to thermal oxidation, the polysilicon is completely converted into a conformal (poly) silicon oxide layer having a thickness about 2.5 times that of the polysilicon layer. The resulting (poly) silicon oxide has the conformality of CVD oxide and the high etch resistance of thermally grown oxide.

Abstract: Disclosed is a process for planarization of semiconductor structures having dielectric isolation regions. Specifically, the process is directed to planarization of an organic polyimide layer obtained following filling of deep trenches in a semiconductor substrate having high and low density trench regions with this material. After over-filling the trenches with the polyimide and obtaining a non-planar polyimide layer having a thickness much larger in the low trench density regions than that in the high density regions, a photoresist layer is applied thereover. The photoresist is then controllably exposed using a mask which is the complement or inverse of the mask used for imaging the trench patterns to obtain a thick blockout photoresist mask over the trenches and a thin wetting layer of photoresist over the remainder of the substrate.

Abstract: Disclosed is a screening paste for covering a selected portion of a metallurgical pattern on a substrate while leaving other metallurgy uncovered. The paste is free of polymers and consists, in one example, of 75-80% of a ceramic particulate (such as alumina), 2-8% amorphous fumed silica and 15-20% of linear alcohol. The linear alcohol serves as a vehicle to deliver the solid particles in the paste. In use, after covering the selected portion of the metallurgical pattern with the paste, the alcohol content therein is expelled by subjecting to vacuum treatment at room temperature or heating to a low temperature below about 275.degree. C. thereby obtaining an inert, dry and crack-free protective coating. Upon evaporation of a new metal layer onto the substrate and removal of the protective coating and new metal layer from everywhere except the uncovered metallurgy, the metallurgical pattern is selectively coated with the new metal.

Abstract: A fully isolated dielectric structure for isolating regions of monocrystalline silicon from one another and method for making such structure are described. The structure uses a combination of recessed oxide isolation with pairs of parallel, anisotropic etched trenches which are subsequently oxidized and filled to give complete dielectric isolation for regions of monocrystalline silicon. The anisotropic etching preferably etches a buried N+ sublayer under the mnocrystalline silicon region and then the trench structure is thermally oxidized to consume the remaining N+ layer under the monocrystalline region and to fully isolate the monocrystalline silicon region between pairs of such trenches.

Abstract: Fabrication of a submicron wide single crystal silicon structure protruding from a monolithic silicon body. Starting with a single crystal N silicon body having a P region, an insulator stud of submicron width and length dictated by the limits of lithography is formed on the P region. Using the stud as a mask, the P region is etched forming the top narrow portion having the stud width projecting from the silicon body. On the exposed sides of the top portion oxide walls are formed and the etching continued forming the middle portion of a width exceeding that of the top portion. An oxide-nitride wall is established on the exposed sides of the middle portion and, using the resulting structure as a mask, the etching is continued to completely etch through the P region and a substantial portion of the underlying N silicon body thereby forming a free-standing silicon protrusion structure. Thick oxide walls are formed on the just exposed sides of the silicon.

Abstract: Disclosed is a sputtering apparatus wherein the wafer-holding plate is provided with openings for accommodating wafers therein. Each opening is of a size slightly smaller than that of the wafer and is provided with a peripheral step-shaped recess so that upon mounting the wafer therein the wafer's top surface is flush with the wafer-holding plate and a major portion of its back surface thereof is exposed. Mounted in close proximity to the wafer-mounting plate is a flat heating element which directly and quickly heats the wafers via their exposed back surfaces to the desired metal silicide forming temperature.Disclosed too is a process of forming high quality metal silicide contacts by mounting the wafers covered with a contact mask on a wafer-mounting plate of a sputtering system such that the back surfaces of the wafers are exposed.

Abstract: A device to thermally couple a heat dissipating integrated circuit chip to the heat sink in a thermal conduction module for effective cooling of the chip by minimizing the thermal resistance path from the chip to the sink. The device is a combination of a heat conducting flat based, truncated solid conical disc which is spring loaded on the back of the chip and a heat conductive hat member having an opening with a continuous tapered wall to conformally fit over the truncated conical disc. The gap between the disc and the hat is packed with a thin layer of a high thermal conductivity grease to provide a low interfacial thermal resistance and mechanical flexibility between the disc and the hat. For additional cooling enhancement of the chip, at the interface between the chip back surface and the base of the disc a self-healing alloy having a high thermal conductivity and low melting point is provided.

Abstract: Disclosed is a method of stabilizing and standardizing semiconductor wafers obtained from a plurality of vendor sources for use in both unipolar and bipolar device manufacturing lines. Based on measured initial oxygen concentration, the as-received wafers are grouped into lots. Next, based on measured oxygen precipitation rate of each lot, the wafer lots are grouped into classes, regardless of their vendor origin. Typically, the grouping consists of three classes corresponding to low, intermediate and high oxgen precipitation rate.The wafers of each class are then subjected to a thermal adaptation cycle tailored to the class to generate in each wafer clusters of a concentration corresponding to a predetermined cluster concentration range and a defect-free zone corresponding to a predetermined defect-free zone range. The thermal adaptation cycle is different from class to class, but identical for wafers of a given class.