Abstract: A nonvolatile memory cell having separate regions for programming and erasing. The cells are formed in an array at a face of a semiconductor body, each cell including a source that is part of a source-column line and including a drain that is part of a drain-column line. Each cell has first, second and third sub-channels between source and drain. The conductivity of the first sub-channel of each cell is controlled by a field-plate, which is part of a field-plate-column line, positioned over and insulated from the first sub-channel. The conductivity of each of the second sub-channels is controlled by a floating gate formed over and insulated from the second sub-channel. Each floating gate has a first tunnelling window positioned over the adjacent source-column line and has a second tunnelling window positioned over the adjacent drain-column line. Row lines, including control gates, are positioned over and insulated from the floating gates of the cells for reading, programming and erasing the cells.

Abstract: An electrically erasable, programmable, read-only-memory, floating-gate, metal-oxide-semiconductor transistor constructed in a trench extending through layers of P-type and N-type material formed on a semiconductor substrate. The floating-gate transistor is comprised of two source-drain regions, a channel region, a floating gate, a programming gate, and gate-oxide layers and is characterized by a floating-gate to channel capacitance that is small relative to the programming-gate to floating-gate capacitance, thereby allowing charging of the floating gate using programming and erasing voltages of less magnitude than might otherwise be necessary.

Abstract: A test circuit for determining whether or not fuse-links of an integrated circuit have been opened or closed properly by, for example, a laser device. The test circuit of this invention, in one embodiment, includes a variable impedance, such as a P-channel transistor, connected between a voltage source and an output terminal, the impedance having one value with a first input applied to the variable impedance control terminal and having a second, larger value in response to a second input applied to the variable impedance control terminal. At least one programmable fuse-link and a gate are connected in series between the output terminal and a source of reference potential. A means for providing control inputs to the variable impedance is connected between a test mode input signal and the control terminal of the variable impedance. The means for providing control inputs to the P-channel transistor may include a second, current-mirror-connected P-channel transistor.

Abstract: An array of nonvolatile memory cells are formed at a face of a semiconductor body, the cells including source regions and including drain regions that are part of a common drain column conductor. Each cell has first and second sub-channel regions between source and drain. The conductivity of the first sub-channel regions of each cell is controlled by a field-plate conductor formed over and insulated from the first sub-channel region. The conductivity of each of the second sub-channel regions is controlled by a floating-gate conductor formed over and insulated from the second sub-channel region. A row line, including control gates, is located above and insulated from the floating gates of the cells for reading, programming and erasing the cells. The field-plate conductor switch provides isolation of the cells during programming.

Abstract: The device and process of this invention provide for eliminating reading errors caused by over-erased cells by subsequently applying alternating erasing and programming pulses to the cells of an EEPROM array, starting with relatively high-energy-level erasing and programming voltages, decreasing the energy-level of each of the alternating erasing and programming voltages. The initial, relatively high-energy-level pulses should have sufficient energy to cause all of the cells to be programmed and to cause all of the cells to be over-erased. The energy-levels are decreased until electron transfer between floating gate and a source or drain region ceases. As the energy-levels are decreased, the threshold voltage range of the memory cells is compacted. The final threshold voltages are distributed within a preselected narrow range of positive values that are less than a predetermined wordline select voltage.

Abstract: A biasing circuit for reading a selected cell of an array of semiconductor memory cells in which each cell is coupled to a drain-column line, a source-column line and a wordline, with the selected cell coupled to a selected drain-column line, a selected source-column line, and a selected wordline.

Abstract: An MOS transistor having a vertical channel disposed along the sides of a trench is disclosed. The transistor is formed in an epitaxial layer on a substrate, with the channel region formed within the epitaxial layer by way of ion implantation and diffusion; the ion implantation is done in such a manner that the epitaxial layer is divided into a portion above the channel region (source region) and a portion below the channel region (drain region). A trench is etched to extend through the epitaxial region into the substrate, gate oxide is grown along the sides of the trench, and a polysilicon gate electrode is deposited adjacent the gate oxide along the walls of the trench. The epitaxial layer allows the drain and source regions of the transistor to have substantially equal carrier concentrations, said concentrations being relatively low.

Abstract: The device and process of this invention provide for elininating reading errors caused by over-erased cells by applying flash erasing pulses, then flash programming pulses to the cells of an EEPROM array. The flash erasing pulses are sufficient in strength to over-erase the cells. The flash programming pulses applied to the control gates have the same voltages as those used to program individual cells. The strength of the programming electric field pulses adjacent the floating gates is controlled by applying a biasing voltage to one of the source/drain regions of the cells. The biasing voltage controls the energy level of the programming field pulses such that only enough charge is transferred to the floating gates to cause the threshold voltages of the cells to have positive values less than that of a predetermined wordline select voltage.

Abstract: A contact-free floating-gate non-volatile memory cell array and process with silicided NSAG bitlines and with source/drain regions buried beneath relatively thick silicon oxide. The bitlines have a relatively small resistance, eliminating the need for parallel metallic conductors with numerous bitline contacts. The array has relatively small bitline capacitance and may be constructed having relatively small dimensions. Isolation between wordlines and between bitlines is by thick field oxide regions. A thick field oxide strip separates each ground conductor/bitline pair. Wordlines may be formed from silicided polycrystalline or other material with low resistivity. Coupling of programming and erasing voltages to the floating gate is improved by extending the gates over the thick field oxide and perhaps by using an insulator with relatively high dielectric constant between the control gate and the floating gate. The four sides of the floating gates are defined with a single patterning step.

Abstract: Resistors are used as controlling devices to control the rate at which output buffer transistors are turned OFF and ON to control transient noise.

Abstract: A contact-free floating-gate non-volatile memory cell array and process with silicided NSAG bitlines and with source/drain regions buried beneath relatively thick silicon oxide. The bitlines have a relatively small resistance, eliminating the need for parallel metallic conductors with numerous bitline contacts. The array has relatively small bitline capacitance and may be constructed having relatively small dimensions. Isolation between wordlines and between bitlines is by thick field oxide. Wordlines may be formed from silicided polycrystalline or other material with low resistivity. Coupling of programming and erasing voltages to the floating gate is improved by extending the gates over the thick field oxide and perhaps by using an insulator with relatively high dielectric constant between the control gate and the floating gate. The resulting structure is a dense cross-point array of progammable memory cells.

Abstract: A nonvolatile memory cell having separate regions for programming and erasing. The cells are formed in an array at a face of a semiconductor body, each cell including a source that is part of a source-column line and including a drain that is part of a drain-column line. Each cell has first, second and third sub-channels between source and drain. The conductivity of the first sub-channel of each cell is controlled by a field-plate, which is part of a field-plate-column line, positioned over and insulated from the first sub-channel. The conductivity of each of the second sub-channels is controlled by a floating gate formed over and insulated from the second sub-channel. Each floating gate has a first tunnelling window positioned over the adjacent source-column line and has a second tunnelling window positioned over the adjacent drain-column line. Row lines, including control gates, are positioned over and insulated from the floating gates of the cells for reading, programming and erasing the cells.

Abstract: A contact-free floating-gate non-volatile memory cell array and process with silicided NSAG bitlines and with source/drain regions buried beneath relatively thick silicon oxide. The bitlines have a relatively small resistance, eliminating the need for parallel metallic conductors with numerous bitline contacts. The array has relatively small bitline capacitance and may be constructed having relatively small dimensions. Isolation between wordlines and between bitlines is by thick field oxide regions. A thick field oxide strip separates each ground conductor/bitline pair. Wordlines may be formed from silicided polycrystalline or other material with low resistivity. Coupling of programming and erasing voltages to the floating gate is improved by extending the gates over the thick field oxide and perhaps by using an insulator with relatively high dielectric constant between the control gate and the floating gate. The resulting structure is a dense cross-point array of programmable memory cells.

Abstract: A sense amplifier including a pair of P-conductivity-type current-mirror transistors, a N-conductivity-type reference transistor and a cascode-connected N-conductivity-type transistor and inverter connected according to prior-art. The amplifier also includes a N-conductivity-type pre-charge transistor with source-drain path connected in parallel with the source-drain path of P-conductivity-type mirror load transistor. The gate of the pre-charge transistor is connected to the gate of the N-conductivity-type cascode transistor, which is also connected to the output of cascode inverter.The pre-charge transistor functions to bypass the mirror load transistor when a discharged bitline is selected. As a result, the current charging the bitline capacitance is increased and the time needed for charging is decreased.

Abstract: An electrically-erasable, electrically-programmable ROM or an EEPROM is constructed using a floating-gate transistor with or without a split gate. The floating-gate transistor may have a self-aligned tunnel window of sublithographic dimension positioned on the opposite side of the source from the channel and drain, in a contact-free cell layout, enhancing the ease of manufacture and reducing cell size. In this cell, the bitlines and source/drain regions are buried beneath relatively thick silicon oxide and the floating gate extends over the thick silicon oxide. Programming and erasing are accomplished by causing electrons to tunnel through the oxide in the tunnel window. The tunnel window has a thinner dielectric than the remainder of the oxides under the floating gate to allow Fowler-Nordheim tunneling. Trenches and ditches are used for electrical isolation between individual memory cells, allowing an increase in cell density.

Abstract: A 2-transistor cell (26) comprises buried diffused regions (34, 36 and 38) aligned substantially parallel. Floating gates (40) are aligned substantially perpendicular to the diffused regions (34, 36 and 38). A control gate (42) defines a first channel region between first and second diffused regions (34 and 36) to define a read transistor (30) and a second channel region between second and third diffused regions (36 and 38) to define a program transistor. The read transistor (30) and program transistor (32) may be individually optimized according to their respective functions. Further, tunnel windows (70) may be provided for Fowler-Nordheim tunneling.

Abstract: A nonvolatile memory cell having separate regions for programming and erasing. The cells are formed in an array at a face of a semiconductor body, each cell including a source that is part of a source-column line and including a drain that is part of a drain-column line. Each cell has first and second sub-channels between source and drain. The conductivity of the first sub-channel of each cell is controlled by a field-plate, which is part of a field-plate-column line, positioned over and insulated from the first sub-channel. The conductivity of each of the second sub-channels is controlled by a floating gate formed over and insulated from the second sub-channel. Each floating gate has a first tunnelling window positioned over the adjacent source-column line and has a second tunnelling window positioned over the adjacent drain-column line. Row lines, including control gates, are positioned above and insulated from the floating gates of the cells for reading, programming and erasing the cells.

Abstract: In one embodiment, the pulse-generating circuit includes a triggering field-effect device having a source-drain path connected between a voltage supply and an internal node and having a gate connected to a source of reference potential, a capacitor connected between the voltage supply and the output node, and a detector field-effect device having a source-drain path connected between the output node and the source of reference potential and having a gate connected to the internal node. An optional load device, an optional pull-down device, an optional second capacitor, an optional string of diode-connected devices, and an optional feedback device may be included. Device channel lengths are specified for proper operation. In one embodiment, the circuit includes only a detector field-effect transistor and a load field-effect transistor, the detector transistor having a channel length substantially longer than the channel length of the load transistor.

Abstract: A contact-free floating-gate non-volatile memory cell array and process with silicided NSAG bitlines and with source/drain regions buried beneath relatively thick silicon oxide. The bitlines have a relatively small resistance, eliminating the need for parallel metallic conductors with numerous bitline contacts. The array has relatively small bitline capacitance and may be constructed having relatively small dimensions. Isolation between wordlines and between bitlines is by thick field oxide. Wordlines may be formed from silicided polycrystalline or other material with low resistivity. Coupling of programming and erasing voltages to the floating gate is improved by extending the gates over the thick field oxide and perhaps by using an insulator with relatively high dielectric constant between the control gate and the floating gate. The resulting structure is a dense cross-point array of programmable memory cells.

Abstract: A contact-free floating-gate non-volatile memory cell array and process with silicided NSAG bitlines and with source/drain regions buried beneath relatively thick silicon oxide. The bitlines have a relatively small resistance, eliminating the need for parallel metallic conductors with numerous bitline contacts. The array has relatively small bitline capacitance and may be constructed having relatively small dimensions. Isolation between wordlines and between bitlines is by thick field oxide regions. A thick field oxide strip separates each ground conductor/bitline pair. Wordlines may be formed from silicided polycrystalline or other material with low resistivity. Coupling of programming and erasing voltages to the floating gate is improved by extending the gates over the thick field oxide and perhaps by using an insulator with relatively high dielectric constant between the control gate and the floating gate. The four sides of the floating gates are defined with a single patterning step.