Abstract: An electronic circuit for the detection of required operational speed of one or more integrated circuit semiconductor chips is used in conjunction with an off-the-shelf integrated circuit tester. The tester provides timing, control and a display. Each of the integrated circuit semiconductor chips is provided with a ring oscillator circuit for generating a series of pulses, timed by the tester for a fixed period of time. A counter, formed in each of the semiconductor chips counts the number of pulses generated during the fixed period of time. A number, generated in the tester, indicative of a required speed of operation is set in a latch assembly that is formed in each of the semiconductor chips. A comparator, also formed in each of the semiconductor chips, compares the contents of the latch with the contents of the counter and if the contents of the counter is equal to or larger than the contents of the latch, the tested semiconductor chip is acceptable. A display in the tester indicates the result.
Abstract: A computer system includes a first processor, a second processor, a bus shared by the first processor and the second processor, and a power on reset coordination means for the first processor and the second processor. The power on reset coordination means includes means for resetting the first processor and the second processor, and means for deasserting reset to the first processor and second processor sequentially. It should be noted that in embodiments of the present invention, some "other" processor must be "up" in order to reset the "first" processor or to deassert reset to it.
May 25, 1990
Date of Patent:
December 3, 1991
Dell USA Corporation
Thomas H. Holman, Jr., David R. Lunsford
Abstract: A digital computer system has an I/O command recovery circuit for providing suitable I/O recovery time for any one of a plurality of associated peripheral devices. The circuit, transparent to both software and system execution speed, enables the digital computer system to efficiently run certain software application programs that interface with the peripheral devices and provide timing loops for setting the command recovery time. Those certain software application programs, designed for earlier and slower computer systems, run the timing loops in too short a time to provide the maximum I/O recovery time. The addition of the I/O command recovery circuit provides selectable and suitable recovery times for each of the associated peripheral devices, including no recovery time for those devices not requiring it.
Abstract: A digital computer system having a local cache memory and a system bus also has a subsystem for regulating the effective processing rate of the central processor unit (CPU) of the computer system. A programmable counter/timer is programmed by data from the CPU to provide a periodic pulse of desired periodicity and pulse width for entry into a bus controller. The bus controller arbitrates use of the system bus, sending a request signal to the CPU requesting the CPU to relinquish use of the bus and it receives an acknowledgement signal from the CPU indicating its relinquishment of use of the bus. The local cache memory is flushed through the cache controller to prevent the CPU from using the local cache memory. This causes the CPU to be periodically active when using the system bus and periodically inactive when the system bus is relinquished, thereby establishing the effective processing rate of the CPU as set by the programmable counter/timer.
Abstract: A personal computer system has an I/O channel and a memory channel with a main logic board incorporating both the I/O channel and the memory channel. The computer has eight (8) expansion slots including a dual-purpose expansion slot for providing space for selective connections of I/O devices through the use of full-length logic cards or half-length logic cards being inserted into edge connectors, High speed memory, including memory control, is mounted on the main logic board and expansion memory, controlled by the memory control is mounted on a printed circuit card that is connected to the memory channel in position within the dual-purpose expansion slot, occupying approximately one-half of that slot, thereby enabling the dual-purpose expansion slot to encompass both the expansion memory and a half-length logic card. In another embodiment, the half-length logic card and the memory card within the dual-purpose expansion slot are integrated into a single logic/memory card.
Abstract: A battery-powered lap-top computer has a main battery for ordinarily supplying power to the computer circuitry. A reserve battery is connected through an automatic switch to the circuitry. The circuitry is connected to a pair of contacts and the switch is connected to a contact. The main battery has positive and negative terminals, and a removal terminal which is shorter in length than the positive and negative terminals. When the main battery loses its charge, it is removed by a sliding action which slides the terminals past the contacts, the removal terminal being the first terminal to lose contact. This activates the automatic switch, connecting the reserve battery into the circuitry so that when the positive and negative terminals are no longer contacted, the reserve battery will have been supplying and will continue to supply power to the circuitry. A charged main battery is then installed, deactivating the switch, removing the reserve battery from the circuitry.
Abstract: A hinge assembly has a plurality of rollers which are pressed against an elastic washer by a shaft. The rollers and elastic washer are contained within a cylindrical retainer which is held in a fixed position relative to a first bracket, while the shaft is held in a fixed position relative to a second bracket so that, when either or both the first and second brackets are moved relative to each other, the roller move around the outside diameter of the shaft resisted by the elastic washer, providing a smooth resistance to the movement of the first bracket and/or second bracket relative to the other. An electronic digital device, having a display section with an adjustable viewing angle utilizing the improved hinge assembly, is shown in which the hinge assembly provides a smooth resistance for the movement of the display section relative to the base of the device.
Abstract: An electronic digital computer has a warning facility for indicating activity and operation, or lack of same, of the central processor in the system. It is done by providing a signal indicative of continuing operation of the central processor to activate an indicator circuit. The indicated circuit utilizes an RC circuit for maintaining a high level through a high comparator when the processor is operational. When the central processor becomes non-operational, the capacitor discharges to a point where a low comparator responds, causing the capacitor to begin charging to its high value. The associated circuits, using this feature, maintain an LED in the active stage until such time as there is no signal indicating continuing operation of the central processor, at which time the LED begins an approximate 50% duty cycle resulting in a blinking indicator.
Abstract: An integrated circuit is formed in a semiconductor chip and connected to at least a first source of voltage and at least a second source of voltage, negative with respect to the first source of voltage. A number of integrated circuit components are activated by the first and second sources of voltage and are interconnected to provide desired functions. An integrated circuit capacitive element in the form of the gate capacitance of a field effect transistor and in the form of a reversed biased diode is connected between the first and second sources of voltage to decouple integrated circuit inherent inductance in series with the first and second sources of voltage.
Abstract: A personal computer has a chassis having a plurality of expansion slots in which are mounted optional Input/Output (I/O) expansion cards. At least one first expansion card has a first bracket adapted for connection to a mounting fixture. At least one second expansion card has a second bracket that is not adapted for connection to the mounting fixture. An adapter bracket is provided which is configured to connect to the mounting fixture and also to the second bracket to provide mounting of the second expansion card in one of the expansion card positions.
April 25, 1989
Date of Patent:
May 8, 1990
Dell Corporate Services Corporation
Charles W. Mitchell, Robert G. Rodriquez
Abstract: A uniform memory system for use with symbolic computers has a very large virtual address space. No separate files, not directly addressable in the address space of the virtual memory, exist. A special object, the peristent root, defines memory objects which are relatively permanent, such objects being traceable by pointers from the persistent root. A tombstone mechanism is used to prevent objects from referencing deleted objects.
Abstract: The disclosure relates to a solenoid valve for an air gun which substantially increases the rate at which maximum air flow is achieved. The new valve structure includes a coil actuated plunger, which is preferably solid and formed of a magnetically permeable material and closes an annular 360 degree port opening between the valve inlet and valve outlet when in the unactuated state. This plunger position is maintained by a biasing spring which forces the forward annular sharp plunger edge against a face seal in the nose of the valve, thereby sealing the valve input port from its output port. Upon actuation of the solenoid valve coil, the plunger is moved against the bias of the spring very rapidly, thereby speedily uncovering the channel between inlet and outlet and permitting rapid 360 degree communication between the inlet and outlet to permit maximum air flow therebetween and out of the outlet port.
Abstract: An impact printer has a print ribbon that is divided into horizontal colored strips to enable color printing. A printhead is mounted on a moving carriage that moves across the width of a printing medium upon which the printing is to be deposited. The print ribbon also moves relative to the carriage. A ribbon shift mechanism is configured to include a print ribbon guide, the ribbon shift mechanism being slideably mounted in the carriage to move in a vertical direction relative thereto. A wire matrix printhead is connected to the carriage and has a printing end adjacent the print ribbon. A gear shaft is positioned to engage the gear sections of a pair of racks that are connected to the ribbon shift mechanism and which pass through the carriage. When the gear shaft is turned, the racks are engaged which cause the ribbon shift mechanism, and the print ribbon, to move either up or down thereby presenting a desired color to the printing end of the printhead.
Abstract: A fast ALU=0 circuit is used with a carry-select lookahead ALU. Preliminary ALU=0 signals are derived for each section of the ALU prior to a carry in signal being received by that section. When the carry in signal is received, a final comparison is made with the least significant bit of the section and the final ALU=0 signal generated. The ALU=0 computation is complete one gate delay after the ALU computation is complete.
Abstract: Periodic checkpoints are taken of the state of a computer system and its virtual memory. If a system crash occurs, the machine state can be rolled back to the checkpoint state and normal operation restarted. Pages of virtual memory are timestamped to indicate whether they are included in the checkpoint state. Modifications made after the checkpoint time are discarded when the system state is rolled back to the saved checkpoint state. Some recordkeeping is maintained outside of the virtual memory address space in order to assist with the recovery process.
Abstract: A computer (30) has parallel elementary processors (P1, . . . , PK) interconnected by an optical crossbar switch (32). Multiple groups of processors, each having a separate crossbar switch, are connected by exchange switches. Optical fibers (34) are used to provide high speed communication between the processors and the switch (32). The optical crossbar switch (32) is reconfigurable dynamically. The computer is reconfigurable to provide efficient implementations of signal processing and logical inference computations, including a systolic filter, a fast Fourier transform, a correlator and a matrix-vector multiplier, forward and backward chaining inference machine, and speech recognizer.
Abstract: A garbage collection system for digital computers classifies memory objects into generations. Objects in older generations which need to reference younger generations must do so indirectly through indirection cells located in the older generation. Thus, all pointers into a generation come from younger generations or indirection cells. When a generation is collected, the indirection cells in that generation are defined to be oldspace and collected in the usual manner. Indirection cells of older generations which can point to the generation being collected are processed by a scavenger.The system also includes read and write barriers which function to filter out undesirable pointers based on the classification and volatility of memory regions to which they point or are destined to be stored.
Abstract: A format conversion system for use in digital systems converts digital data words from a fixed point format to a floating point format and vice versa. A two's complement circuit tests the sign bit of a first fixed point digital data word and provides the complement if the word is negative. A code establishing circuit receives the first fixed point digital data word or its complement, detects the number of O's to the left of the most significant one bit and establishes a first code representative thereof. A second code establishing circuit receives the exponent of a first floating point digital data word and provides a second code representative thereof. A mantissa/fixed point determining circuit receives either the first fixed point digital data word, or the mantissa in reverse order, of the first floating point digital data word.
Abstract: The disclosure relates to a method of making a print head and the print head for a dot matrix printer, wherein there is provided a print wire actuator housing, a plurality of print wire actuators disposed in the housing, the actuators being arranged in the housing at points therein defined by (a) locating in a plane N parallel spaced lines, where N is an odd positive integer, (b) locating a point on the (N+1)/2 line from an extreme one of the lines, (c) defining points on a first arc of a circle having a center of curvature in the direction of the point and passing through the odd ones of the N lines at angles of (360 degrees/N).times.A with the (N+1)/2 line, where A is an integer from 0 to N and (d) defining points on a second arc of a circle having a center of curvature in the direction of the point and on the opposite side of the point as the first arc and passing through the even ones of the N lines at angles of (360 degrees/N).times.A with the (N+1)/2 line, where A is an integer from 0 to N.
Abstract: An incremental garbage collector for use in conjunction with a virtual memory, operates on selected generations of an area upon objects which are contained in a semispace, oldspace or newspace, and during the garbage collection process, all accessible objects are copied from the oldspace to the newspace. The garbage collection process occurs in four phases. In the "flip" phase oldspace and newspace of each generation are exchanged. In the "trace" phase, the pointers which are part of a root set of the generation being collected are traced and all oldspace objects referenced by the pointers are copied to newspace, and the pointers in the root set are updated. All copied objects are then "scavenged" to update any pointers in the cells of the copied objects, and to copy to newspace all oldspace objects referenced by those pointers. Finally a "cleaning oldspace" phase is performed as a low-priority background process to purge the entries for the virtual pages on which "obsolete" pointers reside.
June 26, 1986
Date of Patent:
January 10, 1989
Texas Instruments Incorporated
Timothy J. McEntee, Robert W. Bloemer, Donald W. Oxley, Satish M. Thatte