Abstract: A multiple-antenna transceiver in the present invention includes a frame controller and circuitry for transmitting and receiving. The transmitting component includes a sequence selection circuit, a MIMO modulation and coding circuit, and numerous TX RFE and AFE circuits. The receiving component includes a MIMO demodulation and decoding circuit, a sequence separation circuit, and numerous RX RFE and AFE circuits. The frame controller can enable and disable the TX and RX RFE and AFE circuits individually so as to reduce power consumption of the whole system.

Abstract: A receiver includes; a recovery circuit for receiving an input signal, and generating a data signal and a recovery clock; a processing circuit for processing the data signal to generate a processed signal; and a synchronization determining circuit for determining a synchronization state of the recovery clock according to the processed signal and a first reference value. The data signal includes a synchronous pattern, and the first reference value corresponds to at least a portion of a value in the synchronous pattern processed by the processing circuit. A method of the receiver is also disclosed.

Abstract: The equalizer presented includes a first feed-forward equalization module, a second feed-forward equalization module, and a phase error corrector. The first and the second feed-forward equalization modules respectively receives an input real-part component signal and an input imaginary-part component signal of a complex input signal and respectively equalizes the input real-part component signal and the input imaginary-part component signal to generate a first real-part component signal and a first imaginary-part component signal. The phase error corrector is coupled to the first and the second feed-forward equalization modules for adjusting a complex phase corresponding to the first real-part component signal and the first imaginary-part component signal to generate a second real-part component signal and a second imaginary-part component signal according to a phase error information.

Abstract: System and method for decoding digital video data. The decoding system employs hardware accelerators that assist a core processor in performing selected decoding tasks. The hardware accelerators are configurable to support a plurality of existing and future encoding/decoding formats. The accelerators are configurable to support substantially any existing or future encoding/decoding formats that fall into the general class of DCT-based, entropy decoded, block-motion-compensated compression algorithms. The hardware accelerators illustratively comprise a programmable entropy decoder, an inverse quantization module, a inverse discrete cosine transform module, a pixel filter, a motion compensation module and a de-blocking filter. The hardware accelerators function in a decoding pipeline wherein at any given stage in the pipeline, while a given function is being performed on a given macroblock, the next macroblock in the data stream is being worked on by the previous function in the pipeline.

Abstract: A method for decoding a video block in a video picture includes: selecting N motion vectors from M motion vector, wherein the M motion vectors corresponding to at least a video block of at least a reference area; and decoding the video block according to the N motion vectors.

Abstract: A device for allocating a number of taps of a designated finite impulse response filter is disclosed. The device comprises a plurality of designated finite impulse response filters having fixed number of taps, a plurality of allocation finite impulse response filters having fixed number of taps, a control unit and an estimate unit. Depending on intensities of responses to interferences, at least one of the allocation FIR filters may be coupled in series to any one of the designated finite impulse response filters, thereby to provide a signal having excellent quality.

Abstract: Aspects of a method and system for reduced clock feed-through in a phase locked loop are provided. In this regard, a control voltage for controlling a VCO may be generated via a filter comprising at least one switching element clocked via a clock booster circuit and comprising one or more thick oxide transistors to reduce clock feed-through. A first switching element of the filter may be a first transmission gate comprising thick oxide transistors. The first transmission gate may be part of a sample and hold circuit. A DC voltage on an input node of the sample and hold circuit may be periodically reset via a reset switching element, which may comprise thick oxide transistors. The reset switching element may be controlled via a clock booster circuit. The filter may also comprise a buffer having an input stage comprising one or more thick oxide transistors.

Abstract: For a platform level data model for indications based event control and data transfer, a management controller may enable performing indications based management operations that may be based on a management service utilizing CIM Indications model. The management controller may enable communication of indications based messaging and/or data. The indications may be triggered based on events generated and/or triggered in a plurality of managed entities. The events generation may be performed dynamically within the plurality of managed entities, or may be initiated via the management controller. The management controller may enable processing of partially generated indications, via the plurality of managed entities, and/or as pass-through router for full indications processed via the plurality of managed entities.

Abstract: Systems and methods for load balancing and/or fail over are provided. In one embodiment, a server system may include, for example, one or more of the following: a first network interface card (NIC); a second NIC having same layer-3 (L3) address as the first NIC; a first network switch coupled to the first NIC, the first network switch receiving an incoming traffic flow destined for the second NIC; and a second network switch coupled to the second NIC and coupled to the first network switch. The first network switch may determine, for example, whether the incoming traffic flow is destined for the first NIC or is destined for the second network switch.

Abstract: Aspects of a system and method for optimizing memory bandwidth in a video system may comprise examining different combinations of input and output video formats and video processes that occur between the input and output of the video system. For each combination, a desirable memory bandwidth may be determined, where the desirable memory bandwidth may ensure a maximum system data rate is not exceeded. After determining the desirable values for all combinations of input and output video formats, an optimal value may be selected, where the optimal value may ensure that for any of the combinations the maximum system data rate is not exceeded.

Abstract: A master device for an Ethernet system is disclosed. The master device includes a receiver, a buffer, a phase lock loop unit, and a transmitter. The receiver is used for generating phase adjustment data according to transmission data sent by a slave device when the master device operates during a switch mode. The buffer is coupled to the receiver for accumulating the phase adjustment data and outputting a phase adjustment value. The phase lock loop unit is coupled to the buffer for adjusting the phase of an output clock according to the phase adjustment value to maintain a fixed phase difference between the recovery clock and the output clock. The transmitter is used for transmitting initialization data to the slave device according to the output clock.

Abstract: An adjusting method for reducing local oscillation leakage or I/Q mismatch in a receiver includes the steps of: (a) detecting a current extent of local oscillation leakage or I/Q mismatch; (b) determining if an adjusting direction is correct with reference to the current extent of local oscillation leakage or I/Q mismatch thus detected, maintaining the adjusting direction if correct, and reversing the adjusting direction upon determining that the adjusting direction is incorrect; and (c) adjusting a control signal according to the adjusting direction.

Abstract: An electrophoretic display device includes a substrate, an electrophoretic component layer, a first optical adhesive, a barrier layer, a second optical adhesive, a protective layer, and a sealant. The first optical adhesive and the second optical adhesive contribute in helping to provide light exposure to the sealant. One of the first optical adhesive and the second optical adhesive is capable of absorbing the light of predetermined wavelength and is adapted to expose the sealant.

Abstract: A cushioning structure includes a main body and two first cushioning elements. The first cushioning elements clip two ends of the main body, respectively, to form a containing space. Each of the first cushioning elements has two symmetrical cushioning portions for sandwiching the main body. Each of the cushioning portions has an inclined plane extending inward from an edge of the main body.

Abstract: Embodiments of the present disclosure provide for processes for manufacture of a dry strength paper, methods for imparting dry strength to paper using a cationic starch graft polymer, and the like.

Abstract: A backlight driving method, which provides three kinds of light sources comprising a red light source, a blue light source, and a green light source. The driving method includes dividing a frame into four sub-frames, and lighting the green light sources twice during two sub-frames respectively, dividing the first frame and the second frame into four sub-frames respectively, lighting the four light sources in the four sub-frames in a first lighting order during the first frame, and lighting the four light sources in the four sub-frames using a second lighting order during the second frame, wherein the first order is different from the second order.

Abstract: One embodiment comprises a transmitter precoder operating on an input signal to produce an output signal for modulation. The output signal is transmitted using a constellation with a constellation density. The transmitter precoder comprises scaler logic, precoder logic and selection logic. The scaler logic scales the input signal to maintain constant power on the input signal independent of the constellation density. The precoder logic precodes the scaled signal to produce a dither signal limited to a range of values. The range is inversely proportional to the constellation density. The selection logic is operable in two states. In the first state, the selection logic combines the scaled signal with the dither signal to produce the output signal. In the second state, the selection provides the scaled signal as the output signal.

Abstract: The present invention provides for a system and method for blocking leakage signals and uncoupling connections in a communication system. A leakage signal (LS) blocking splitter employs a high-pass filter which effectively blocks the lower frequency leakage signal. The high-pass filter (an LS filter) has a cut-off frequency selected to fall between the upper range of the leakage signal (which is approximately 4 KHz in the preferred embodiment) and the low-end frequency of a data signal. A detect and terminate function detects service on the communication connection to which each one of the leakage signal (LS) filters are coupled to. The detect and terminate function detects service on the communication connection to ensure that each LS blocking splitter is coupled to an in-service communication connection.

Abstract: The present invention is directed to the synthesis and stabilization of neutral molecules containing homonuclear single or multiple bonds, methods of preparation, and uses thereof.

Abstract: Embodiments of the present disclosure provide for methods of studying (e.g., detecting, localizing, and/or quantifying) biomarker(s) and the like.