Patents Represented by Attorney Thomas R. FitzGerald, Esq.
  • Patent number: 7971685
    Abstract: The invention comprises, in one form thereof, a pump jack tree stand including a platform and a seat engaging a pump jack. The pump jack cooperates with a pole that is supported by an adjacent tree. The user actuates a foot lever on the pump jack to climb the pole. The pump jack's release is hand actuated as opposed to the commonly used foot-actuated release.
    Type: Grant
    Filed: February 1, 2007
    Date of Patent: July 5, 2011
    Inventors: Anthony Simone, Frank Garcea
  • Patent number: 7602017
    Abstract: Low voltage, middle voltage and high voltage CMOS devices have upper buffer layers of the same conductivity type as the sources and drains that extend under the sources and drains and the gates but not past the middle of the gates, and lower bulk buffer layers of the opposite conductivity type to the upper buffer layers extend from under the upper buffer layers to past the middle of the gates forming an overlap of the two bulk buffer layers under the gates. The upper buffer layers and the lower bulk buffer layers can be implanted for both the NMOS and PMOS FETs using two masking layers. For middle voltage and high voltage devices the upper buffer layers together with the lower bulk buffer layers provide a resurf region.
    Type: Grant
    Filed: March 13, 2007
    Date of Patent: October 13, 2009
    Assignee: Fairchild Semiconductor Corporation
    Inventor: Jun Cai
  • Patent number: 7031391
    Abstract: A narrowband video codec for generating an output stream of control, data, and error correction bits includes means for framing the outputs control and data bits into a series of sequential frames of bytes for transmission over an RF link of a controlled frequency. Each frame includes an identical sequence of bytes. Each frame of bytes includes, in sequence, two control bytes, a plurality of sequential sets of data bytes, and a plurality of error correction bytes. Each set of data bytes includes a sequence of at least one audio byte and a plurality of video bytes. At least one video byte is between each sequential audio byte. Each set of data bytes has its audio and video bytes in the same order as each other set of data bytes.
    Type: Grant
    Filed: February 18, 1997
    Date of Patent: April 18, 2006
    Assignee: Harris Corporation
    Inventor: Robert Keith Riffee
  • Patent number: 7005353
    Abstract: A method for reducing miller capacitance and switching losses in an integrated circuit includes providing a switching gate electrode having respective portions that are coplanar with the source and well regions of the integrated circuit. The switching gate electrode is configured for switching the integrated circuit on and off in response to a relatively small change in applied voltage. A shielding gate electrode is formed with respective portions coplanar with the switching electrode and the well region. The shielding electrode is configured for charging the gate-to-drain overlap region of the integrated circuit.
    Type: Grant
    Filed: February 7, 2005
    Date of Patent: February 28, 2006
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Christopher B. Kocon, Alan Elbanhawy
  • Patent number: 6955978
    Abstract: A semiconductor device can comprise a contact material in substantially continuous contact with a contact region. In an embodiment the contact region may comprise an alloy comprising a wide band-gap material and a low melting point contact material. A wide band-gap material may comprise silicon carbide and a low melting point contact material may comprise aluminum. In another embodiment a substantially uniform ohmic contact may be formed between a contact material and a semiconductor material by annealing the contact at a temperature less than the melting point of the contact material. In an embodiment, the contact may be annealed for more than five hours.
    Type: Grant
    Filed: December 20, 2001
    Date of Patent: October 18, 2005
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Richard L. Woodin, William F. Seng
  • Patent number: 6946348
    Abstract: Merging together the drift regions in a low-power trench MOSFET device via a dopant implant through the bottom of the trench permits use of a very small cell pitch, resulting in a very high channel density and a uniformly doped channel and a consequent significant reduction in the channel resistance. By properly choosing the implant dose and the annealing parameters of the drift region, the channel length of the device can be closely controlled, and the channel doping may be made highly uniform. In comparison with a conventional device, the threshold voltage is reduced, the channel resistance is lowered, and the drift region on-resistance is also lowered. Implementing the merged drift regions requires incorporation of a new edge termination design, so that the PN junction formed by the P epi-layer and the N+ substrate can be terminated at the edge of the die.
    Type: Grant
    Filed: March 5, 2004
    Date of Patent: September 20, 2005
    Assignee: Fairchild Semiconductor Corporation
    Inventor: Jun Zeng
  • Patent number: 6929988
    Abstract: The cellular structure of the power device includes a substrate that has a highly doped drain region. Over the substrate there is a more lightly doped epitaxial layer of the same doping. Above the epitaxial layer is a well region formed of an opposite type doping. Covering the wells is an upper source layer of the first conductivity type that is heavily doped. The trench structure includes a sidewall oxide or other suitable insulating material that covers the sidewalls of the trench. The bottom of the trench is filled with a doped polysilicon shield. An interlevel dielectric such as silicon nitride covers the shield. The gate region is formed by another layer of doped polysilicon. A second interlevel dielectric, typically borophosphosilicate glass (BPSG) covers the gate. In operation, current flows vertically between the source and the drain through a channel in the well when a suitable voltage is applied to the gate.
    Type: Grant
    Filed: October 1, 2003
    Date of Patent: August 16, 2005
    Assignee: Fairchild Semiconductor Corporation
    Inventor: Jun Zeng
  • Patent number: 6909139
    Abstract: An integrated circuit has a high voltage area, a logic area and a memory array for forming a system on a chip that includes linear, logic and memory devices. The memory array has floating gate transistors disposed in a triple well structure with a raised drain bit line 13 substantially vertically aligned with a buried source bit line 14. The memory array separates the columns with deep trenches 46 that may also be formed into charge pump capacitors.
    Type: Grant
    Filed: June 27, 2003
    Date of Patent: June 21, 2005
    Assignee: Infineon Technologies AG
    Inventors: Danny Shum, Georg Tempel, Ronald Kakoschke
  • Patent number: 6909143
    Abstract: A lateral double-diffused MOS (LDMOS) transistor is provided. The LDMOS transistor includes a semiconductor substrate 202 formed of a material having p-conductivity type impurities, a drift region formed of a material having n-conductivity type impurities on the semiconductor substrate, a first buried layer 206 of p-type material and a second buried layer 208 formed of n-type material. Layers 206 and 208 are arranged at the boundary between the semiconductor substrate and the drift region. A first well region 210 of p-type material contacts the first buried layer 206 n-type in a first portion 1 of the drift region.
    Type: Grant
    Filed: April 2, 2004
    Date of Patent: June 21, 2005
    Assignee: Fairchild Korea Semiconductor
    Inventors: Chang-Ki Jeon, Jong-Jib Kim, Young-Suk Choi
  • Patent number: 6906362
    Abstract: An integrated circuit die includes an active area having source dopants and contacts. An active area metal layer overlies the active area. A sense area is disposed on the die. A sense area metal layer overlies the sense area. A plurality of polysilicon gate stripes, polysilicon openings, and body stripes are disposed on the die, and extend in a continuous and uninterrupted manner from the active area into the sense area. A first region from which source dopants and contacts have been excluded surrounds a periphery of the sense area. An etched region is disposed over the first region, thereby separating and electrically isolating the sense area metal layer from the active area metal layer.
    Type: Grant
    Filed: December 10, 2002
    Date of Patent: June 14, 2005
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Joseph A. Yedinak, Dwayne S. Reichl, Douglas J. Lange
  • Patent number: 6890155
    Abstract: A fan blade has a three dimensional shape that resembles a leaf. The blade is made of balsa or other suitable wood with the grain of the wood running along its length. The obverse surface of the blade is contoured and has a central vein and lateral veins running from the central vein to opposite edges. The reverse side has one or more channels. Braces are set in the channels. The braces are also made of balsa or comparable wood and their grain runs transverse to the direction of the gain of the blade.
    Type: Grant
    Filed: September 11, 2002
    Date of Patent: May 10, 2005
    Inventor: Thomas Cartwright
  • Patent number: 6873017
    Abstract: Device 60 in FIG. 3 has junctions 86 each with a lateral portion 90 and a second portion 92 extending upward toward the surface 12 from the lateral portion 90. The lateral portions 90, as illustrated in FIG. 3, are more or less formed along a plane parallel with the surface 12. The upwardly extending portions 92 include characteristic curved edges of the diffusion fronts which are associated with the planar process. With the regions 80 and 82 each having relatively high net dopant concentrations of different conductivity types, each lateral junction portion 90 includes a relatively large sub region 96 which extends more deeply into the layer 10. When compared to other portions of the junctions 86, the subregions 96 are characterized by a relatively low breakdown voltage so that ESD current is initially directed vertically rather than laterally.
    Type: Grant
    Filed: May 14, 2003
    Date of Patent: March 29, 2005
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Jun Cai, Alvin Sugerman, Steven Park
  • Patent number: 6871359
    Abstract: The present invention relates to an inner cloth for a glove which is inserted between a lining material contacting with a user's skin and an outer skin exposed to the outside and includes a certain connection member for thereby being fixed together with a lining material and an outer skin based on a sewing operation, so that it is possible to implement good moisture penetration, anti-cold, and waterproof functions. The inner cloth for a glove includes a pair of hand-shaped panel members which each include a certain size or area and an edge portion connected at a certain width, and a connection member which is arranged at a certain position of the pair of the panel members and is integrally formed when the panel members are connected, and is formed in a certain shape. The glove implements good moisture penetration, anti-cold and waterproof functions using the inner cloth of the present invention.
    Type: Grant
    Filed: September 4, 2002
    Date of Patent: March 29, 2005
    Inventor: Dong Sik Han
  • Patent number: 6870218
    Abstract: A semiconductor integrated circuit including an LDMOS device structure includes a semiconductor layer with a pair of spaced-apart field effect gate structures over an upper surface of the semiconductor layer. First and second spaced-apart source regions of a first conductivity type are formed in a portion of the layer between the pair of gate structures with a first region of a second conductivity type formed there between. A lightly doped body region of a second conductivity type is formed in the semiconductor layer, extending from below the source regions to below the gate structures and extending a variable depth into the semiconductor layer. This body region is characterized by an inflection in depth in that portion of the body region extending below the first region.
    Type: Grant
    Filed: December 10, 2002
    Date of Patent: March 22, 2005
    Assignee: Fairchild Semiconductor Corporation
    Inventor: Jun Cai
  • Patent number: 6870217
    Abstract: A method of driving a dual-gated MOSFET having a Miller capacitance between the MOSFET gate and drain includes preparing the MOSFET to switch from a blocking mode to a conduction mode by applying to the MOSFET shielding gate a first voltage signal having a first voltage level. The first voltage level is selected to charge the Miller capacitance and thereby reduce switching losses. A second voltage signal is applied to the switching gate to switch the MOSFET from the blocking to the conduction mode. The first voltage signal is then changed to a level selected to reduce the conduction mode drain-to-source resistance and thereby reduce conduction losses. The first voltage signal is returned to the first voltage level to prepare the MOSFET for being switched from the conduction mode to the blocking mode.
    Type: Grant
    Filed: October 16, 2003
    Date of Patent: March 22, 2005
    Assignee: Fairchild Semiconductor Corporation
    Inventor: Alan Elbanhawy
  • Patent number: 6849496
    Abstract: A semiconductor Dynamic Random Access Memory (DRAM) cell is fabricated using a vertical access transistor and a storage capacitor formed in a vertical trench. A Shallow Trench Isolation (STI) region is used as a masking region to confine the channel region of the access transistor, the first and second output regions of the access transistor, and a strap region connecting the second output region to the storage capacitor, to a narrow portion of the trench. The so confined second output region of the access transistor has reduced leakage to similar second output regions of adjacent memory cells. Adjacent memory cells can then be placed closer to one another without an increase in leakage and cross-talk between adjacent memory cells.
    Type: Grant
    Filed: July 11, 2003
    Date of Patent: February 1, 2005
    Assignee: Infineon Technologies AG
    Inventors: Venkatachalam C. Jaiprakash, Mihel Seitz, Norbert Arnold
  • Patent number: 6847911
    Abstract: A method of throttling the frequency with which an integrated circuit is accessed includes sensing the temperature of the integrated circuit die and converting the sensed temperature to a digital signal. The digital signal is stored in a register of the integrated circuit. The digital signal is read, and the frequency with which the integrated circuit is accessed is adjusted dependent at least in part upon the temperature of the die as indicated by the digital signal.
    Type: Grant
    Filed: August 2, 2002
    Date of Patent: January 25, 2005
    Assignee: Infineon Technologies AG
    Inventors: Jennifer Faye Huckaby, Torsten Partsch, Johnathan Edmonds
  • Patent number: 6841824
    Abstract: A process and product for making integrated circuits with dense logic and/or linear regions and dense memory regions is disclosed. On a common substrate, a dual hard mask process separately forms stacks of logic and/or linear transistors and EEPROM memory transistors. By using the process, the logic and/or linear and memory transistors are made with different sidewall insulating layers. The logic and/or linear transistors have relatively thin sidewall insulating layers sufficient to provide isolation from adjacent devices and conductors. The memory transistors have thicker sidewall insulating layer to prevent the charge stored in the memory device from adversely influencing the operation of the memory transistor.
    Type: Grant
    Filed: September 4, 2002
    Date of Patent: January 11, 2005
    Assignee: Infineon Technologies AG
    Inventor: Danny Shum
  • Patent number: 6833585
    Abstract: A high voltage lateral Double diffused Metal Oxide Semiconductor (DMOS) transistor includes a plurality of well regions of a first conductivity type formed to be spaced out within a well region of a second conductivity type between a channel region of the first conductivity type and a drain region of the second conductivity type. Most current is carried through some portions of the well region of the second conductivity type in which the well regions of the first conductivity do not appear so that the current carrying performance of the device is improved. When a bias voltage is applied to the drain region, the well region of the second conductivity type is completely depleted at other portions where the well region of the second conductivity type and the well regions of the first conductivity type alternately appear so that the breakdown voltage of the device can be increased.
    Type: Grant
    Filed: April 10, 2002
    Date of Patent: December 21, 2004
    Assignee: Fairchild Korea Semiconductor
    Inventors: Min-hwan Kim, Chang-ki Jeon, Young-suk Choi
  • Patent number: 6831329
    Abstract: A quick punch-through integrated gate bipolar transistor (IGBT) includes a drift region and a gate. The drift region has a drift region dopant concentration and a drift region thickness. The gate has a gate capacitance. The drift region dopant concentration, drift region thickness and gate capacitance are adjusted dependent at least in part upon the PNP gain of the IGBT to maintain the potential difference between the gate and emitter at a level greater than the IGBT threshold voltage when the collector voltage reaches the bus voltage. This insures that the hole carrier concentration remains approximately equal to or greater than the drift region dopant concentration when the depletion layer punches through to the buffer region during the turn-off delay. Thus, the collector voltage overshoot and the rate of change of voltage and current are controlled, and electromagnetic interference is reduced, during turn off.
    Type: Grant
    Filed: October 22, 2002
    Date of Patent: December 14, 2004
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Joseph A. Yedinak, Jon Gladish, Sampat Shekhawat, Gary M. Dolny, Praveen Muraleedharan Shenoy, Douglas Joseph Lange, Mark L. Rinehimer