Abstract: A visual pattern of insulating material is used to guide visually the placement of test probes on a semiconductor wafer. A passivation layer is patterned over the probed areas on the wafer, and then planarized. Planarization of the passivation layer permits reliable addition and retention of an acceptable layer of under bump metal over the planarization after probing is completed. Acceptable test probing of semiconductor device pads may thus be performed before bump connections are fabricated. Each wafer that does not pass testing is eliminated from the bump fabrication process, saving the cost of fabricating bumps on an unusable wafer.
Abstract: A converter 10 has an IGBT power switch 34. A resonant tank circuit 30 couples the IGBT to a voltage source. A gate controller turns the IGBT on and off by applying a suitable gate control voltage to the gate. The resonant tank circuit imposes a sinusoidal waveform on the emitter current. After the emitter current reverses direction, the gate signal is terminated and the IGBT is shut off. Minority carriers in the emitter are swept away by the tank circuit and are further deposited in a transformer that is coupled to the tank circuit.
Abstract: A process for filling a trench having sidewalls and a floor in a semiconductor device or integrated circuit comprises: forming an insulating layer on the sidewalls and floor of a trench in a semiconductor substrate, substantially filling the trench with semiconductor material, removing semiconductor material from an upper portion of the trench, depositing a first layer of BPSG in the upper portion of the trench, heating the substrate to a first temperature greater than about 850° C. and up to about 1100° C., depositing a second layer of BPSG above the first layer of BPSG, and heating the substrate to a second temperature greater than about 850° C. and up to about 1100° C. The first and second BPSG layers each comprises boron and phosphorus in a weight ratio of boron: phosphorus of greater than 1:1.
Type:
Grant
Filed:
February 26, 2002
Date of Patent:
October 15, 2002
Assignee:
Fairchild Semiconductor Corporation
Inventors:
Rodney S. Ridley, Frank Stensney, John L. Benjamin, Jack H. Linn
Abstract: The invention relates in general to a method and apparatus for locking one element to another with a gimbal lock without castoring about a gimbal axis. In one preferred embodiment, a mounting apparatus and method for a roller transfer assembly for use in a reproduction apparatus are provided that accurately positions the roller transfer assembly in operative relation with a dielectric member of a reproduction apparatus with an anti-castor gimbal locking coupling.
Type:
Grant
Filed:
February 26, 2001
Date of Patent:
October 15, 2002
Assignee:
Heidelberg Digital L.L.C.
Inventors:
George R. Walgrove, III, Gary B. Bertram, Daniel R. Palmer
Abstract: A method and apparatus for identifying the root causes of image artifacts visible in the printed output of an electrophotographic printer, activating a special operating mode for the marking engine, and referencing the printing process intentionally to each rotating member of the electrophotographic process in turn. The referencing insures that image artifacts and/or non-uniformities originating from each rotating member are visible in the same location on each printed output. Since the rotating members employed are intentionally designed to be different in diameter, the referencing of the printing process to each one of the rotating members in conjunction with variable receiver sizes enables an operator to associate each image artifact or non-uniformity with a specific rotating member causing it. The appearance of image artifacts is enhanced through zero offset voltage printing and flat-field exposure of the rotating member images as appropriate.