Abstract: Various method and apparatus for packaging an integrated circuit are provided. In one aspect, a method of packaging an integrated circuit is provided that includes coupling an integrated circuit to a substrate, mixing an adhesive with a plurality of particles, and coupling a lid to the substrate with the adhesive. At least a portion of the plurality of particles in the adhesive oppose compressive force from the lid to restrict rotation of the lid relative to the substrate.

Abstract: Various devices for measuring an electronic device lid are provided. In one aspect, an apparatus is provided that includes an integrated circuit, a lid for positioning on the integrated circuit, and a junction of two dissimilar metals associated with the lid. The junction provides a thermocouple to provide an output signal representative of a temperature of the lid.

Abstract: Various integrated circuit package elements are provided. In one aspect, an integrated circuit package device is provided that includes a lid for covering an integrated circuit. The lid has a convex surface for applying pressure on the integrated circuit when the lid is placed in a selected position. In another aspect, an integrated circuit package device is provided that includes a lid that has a surface for applying pressure to an integrated circuit when the lid is in a selected position. A gold film is coupled to the surface. The gold film has a periphery and a plurality of rounds extending from the periphery.

Abstract: Double-sided waffle packs and methods of using the same are provided. In one aspect, a waffle pack is provided that includes a body that has a first side and second side opposite the first side. The first side has a first cavity for enabling a semiconductor die to be seated therein when the body is in a first orientation. The second side has a second cavity for enabling a semiconductor die to be seated therein when the body is in a second orientation opposite the first orientation. The first cavity has a first footprint and the second cavity has a second footprint. The first and second footprints are substantially aligned vertically.

Abstract: Methods and apparatus for checking layouts of circuit features are provided. In one aspect, a method of designing a layout for a circuit feature is provided that includes deriving a function which relates a size and a plurality of aerial image parameters of the circuit feature to a probability of a printing fault in using a lithographic process to pattern the circuit feature. A layout for the circuit feature is created. The function is used to determine a probability of a printing fault in using the lithographic process to pattern the circuit feature and adjust the layout of the circuit feature as necessary in view of the determined probability of printing fault.

Abstract: A test structure and methods of using and making the same are provided. In one aspect, a test structure is provided that includes a first conductor that has a first end and a second conductor that has a second end positioned above the first end. A third conductor is positioned between the first end of the first conductor and the second end of the second conductor. A first electrode is coupled to the first conductor at a first distance from the third conductor and a second electrode coupled to the first conductor at a second distance from the third conductor. A third electrode is coupled to the second conductor at a third distance from the third conductor and a fourth electrode is coupled to the second conductor at a fourth distance from the third conductor. The first through fourth electrodes provide voltage sense taps and the first and second conductors provide current sense taps from which the resistance of the third conductor may be derived.

Abstract: An integrated circuit lid fixture and methods of using the same are provided. In one aspect, an integrated circuit lid fixture is provided that includes a base that has a plurality of pillars. Each of the plurality of pillars has a surface for supporting a substrate that may be removably seated thereon. The surfaces of the plurality of pillars have a first footprint at least as large as a footprint of the substrates to be placed thereon. A plate is provided for applying a compressive force to an integrated circuit lid positioned on any of the substrates removably seated on the pillars.

Abstract: Methods of fabricating halo regions are provided. In one aspect, a method is provided of fabricating a first halo region and a second halo region for a circuit device of a first conductivity type and having a gate structure with first and second sidewalls. The first halo region of a second conductivity type is formed by implanting the substrate with impurities in a first direction toward the first sidewall of the gate structure. The second halo region of the second conductivity type is formed by implanting the substrate with impurities in a second direction toward the second sidewall of the gate structure. The first and second halo regions are formed without implanting impurities in a direction substantially perpendicular to the first and second directions.

Abstract: Various methods of fabricating halo regions are disclosed. In one aspect, a method of manufacturing is provided that includes forming a symmetric transistor gate and an asymmetric transistor gate on a substrate. The symmetric and asymmetric transistor gates are substantially perpendicular. A mask is formed on the substrate with a first opening and a second opening. The first opening is sized to enable implantation of first and second halo regions beneath the symmetric transistor gate. The second opening is sized to enable implantation of a third halo region beneath and on one but not both sides of the asymmetric gate. The first and second halo regions are formed beneath the first gate by implanting through the first opening toward opposite sides of the symmetric gate. The third halo region is formed beneath and proximate one but not both sides of the asymmetric transistor gate by implanting through the second opening.

Abstract: Various probe systems and probes are provided. In one aspect, a probe is provided that includes a base and a first member coupled to the base. The first member has a first tip for probing a circuit device. A first actuator is coupled to the first member for moving the first member relative to the base. Electrical and/or topographical probing is possible.

Abstract: Various wires and methods of making the same are disclosed. In one aspect, a wire is provided that includes a core and a tube around the core. The tube is composed of an alloy containing about 33 to 37% nickel, about 31.5 to 39% cobalt, about 9 to 10.5% molybdenum, and about 19 to 21% chromium. The wire has an ultimate tensile strength of about 150 to 250 kpsi, an amount of cold work following a final anneal and a torsional ductility of greater than about 6 turns-to-failure per inch of the wire.

Abstract: Various devices for mounting circuit devices and methods of making the same are provided. In aspect, a device is provided that includes a member for holding an integrated circuit. The member contains a first plurality of carbon nanotubes to enhance the thermal conductivity thereof. At least one conductor member projects from the member. In another aspect, a method of fabricating an interface for an electronic component is provided that includes forming a member containing a first plurality of carbon nanotubes and forming at least one conductor on the member.

Abstract: Various methods of fabricating halo regions are disclosed. In one aspect, a method of manufacturing is provided that includes forming a symmetric transistor and an asymmetric transistor on a substrate. A first mask is formed on the substrate with a first opening to enable implantation formation of first and second halo regions proximate first and second source/drain regions of the symmetric transistor. First and second halo regions of a first dosage are formed beneath the first gate by implanting off-axis through the first opening. A second mask is formed on the substrate with a second opening to enable implantation formation of a third halo region proximate a source region of the second asymmetric transistor while preventing formation of a halo region proximate a drain region of the asymmetric transistor. A third halo region of a second dosage greater than the first dosage is formed by implanting off-axis through the second opening.

Abstract: Apparatus for and methods of inspection using laser beam induced alteration are provided. In one aspect, an apparatus is provided that includes a laser scanning microscope for directing a laser beam at a circuit structure and a source for biasing and thereby establishing a power condition in the circuit structure. A detection circuit is provided for detecting a change in the power condition in response to illumination of the circuit structure by the laser beam and generating a first output signal based on the detected change. A signal processor is provided for processing the first output signal and generating a second output signal based thereon. A control system is operable to scan the laser beam according to a pattern that has a plurality of pixel locations, whereby the laser beam may be moved to a given pixel location and allowed to dwell there for a selected time before being moved to another pixel location.

Abstract: Various apparatus and methods for enhancing hot-electron luminescence in an integrated circuit are provided. In one aspect, an apparatus is provided that includes a first circuit device coupled to a first voltage source that is operable to bias the first circuit device to a first voltage, and a second circuit device that has a first input coupled to the first voltage source and a junction defining a first side and a second side. One of the first and second sides is coupled to a second voltage source that is independent of the first voltage source and capable of selectively biasing the one of the first and second sides at a second voltage higher than the first voltage. The second device is operable to emit a hot-electron induced photon upon entry into saturation.

Abstract: Various embodiments of a golf device for use on a putting surface are provided. In one aspect, a golf device for use on a putting surface is provided that includes a ball that has a center and a first outer diameter. First and second annular members are coupled to the ball in substantially parallel spaced-apart relation. The spacing of the first and second annular members defines a spherical zone of the ball that projects radially outwardly from the center beyond the outer peripheral surfaces of the first and second annular members. The first and second diameters of the first and second annular members are sized so that a first portion of the first outer peripheral surface and a second portion of the second outer peripheral surface are positioned substantially at the putting surface. The device provides rapid tactile and visual feedback of a misstroke.

Abstract: Various embodiments of a semiconductor-on-insulator substrate incorporating a Peltier effect heat transfer device and methods of fabricating the same are provided. In one aspect, a circuit device is provided that includes an insulating substrate, a semiconductor structure positioned on the insulating substrate and a Peltier effect heat transfer device coupled to the insulating substrate to transfer heat between the semiconductor structure and the insulating substrate.

Abstract: Various microscopy probes and methods of fabricating the same are provided. In one aspect, a method of fabricating a microscopy probe is provided that includes providing a member and forming a first film on the member. The first film fosters growth of carbon nanotubes when exposed to a carbon-containing compound. A second film is formed on the first film. The second film has an opening therein that exposes a portion of the first film. A carbon nanotube is formed on the exposed portion of the first film.

Abstract: Various embodiments of a planarization device and methods of using the same are provided. In one aspect, a device for planarizing a surface of a semiconductor workpiece is provided that includes a table for holding a quantity of an electrically conducting solution thereon. A member is included for holding the semiconductor workpiece such that the surface is in contact with the solution and operates as a working electrode. The member has a first conductor for establishing electrical connection with the semiconductor workpiece. A counter electrode is provided for making electrical connection with the solution and a reference electrode is provided for making electrical connection with the solution with a known electrode potential. A power source is operable to control the electric potential between the working electrode and the counter electrode. Slurry consumption may be dramatically reduced and static etch rate due to aborts may be virtually eliminated.

Abstract: Methods and apparatus for inspecting a sample are provided. In one aspect, a method of inspection is provided that includes generating an entangled set of particle beams and directing one of the entangled set of particle beams to a location of a workpiece. One of the entangled set of particle beams interacts with the location of the workpiece. One of the entangled set of particle beams is observed after the interaction with the location of the workpiece to inspect the location of the workpiece.