Abstract: A programmable serial data path includes a programmable timing circuit and a parallel to serial module. The programmable timing circuit is operably coupled to generate a first plurality of timing signals when width of parallel input data is of a first multiple and to generate a second plurality of timing signals when the width of the parallel input data is of a second multiple. The parallel to serial module is operably coupled to convert the parallel input data into serial output data based on the first or second plurality of timing signals.

Abstract: A Transmit line driver with selectable pre-emphasis and driver signal magnitudes comprises a primary current driver for setting a primary current level and a pre-emphasis current driver that provides an additional amount of current that is superimposed with or added to the primary current level produced by the primary current driver. The pre-emphasis current has either negative or positive magnitude based upon a pre-emphasis signal logic state. A first current selection module defines a reference signal that is used to select the primary current driver output signal magnitude in a first current mirror, while a second current selection module is used to define a second reference signal that selects a pre-emphasis current driver signal magnitude in a second current mirror. Logic generates a binary signal to both the first and second current selection modules to select the current levels as well as the pre-emphasis signal.

Abstract: A frequency multiplier and amplification circuit are disclosed. One embodiment of the present invention comprises: a multiplier operably coupled to multiply a first sinusoidal waveform having a first frequency with a second sinusoidal waveform having a second frequency to produce a third sinusoidal waveform, having a frequency representative of a difference between the first frequency and the second frequency, and a fourth sinusoidal waveform having a frequency representative of a sum of the first and second frequencies; and a frequency-tuned load operably coupled to substantially attenuate the third sinusoidal waveform and to substantially pass the fourth sinusoidal waveform as an output of the frequency-tuned multiplier circuit. The frequency-tuned multiplier circuit can be a single-ended multiplier circuit or a differential multiplier circuit with corresponding single-ended or differential first and second sinusoidal waveforms.

Abstract: A method and apparatus for generating a self-correcting local oscillation includes processing that begins by generating a synthesized frequency from a reference frequency. The processing then continues by dividing the synthesized frequency by a divider value to produce a divided frequency. The processing continues by generating an auxiliary frequency and mixing the auxiliary frequency with the divided frequency to produce a corrected frequency. The processing then continues by mixing the corrected frequency with the synthesized frequency to produce a local oscillation.

Abstract: A signal power detector includes an input coupling circuit and a rectifying operational amplifier. The input coupling circuit is operably coupled to receive a signal and to convert the signal into a first input and a rectifying input. The rectifying operational amplifier is operably coupled to receive the first input and the rectifying input and to produce therefrom a rectified output signal that represents a peak of the received signal.

Abstract: Calibration of received signal strength indication (RSSI) within a radio frequency integrated circuit (RFIC) begins by concurrently enables a transmitter portion and receiver portion. With both the transmitter and receiver enabled, the RFIC provides a zero input to the transmitter portion, where the zero input is an effective zero input based on the input circuitry of the transmitter portion. The RFIC then measures, via the receiver portion, the received signal strength of the RF signal generated by the transmitter portion regarding the zero input signal. The RFIC then compares the measured received signal strength with a desired zero input signal strength value. If the measured received signal strength compares unfavorably with the desired zero input signal strength value (e.g.

Abstract: A method and apparatus for managing an optical transceiver includes processing that begins by transceiving management data with modules external to the optical transceiver. The processing then continues by converting the management data transceived with the external modules between a 1st data format (e.g., MDIO interface compatible) and a generic data format (e.g., a format convenient for reading data to and writing data from a random access memory). The processing continues by transceiving management data with modules internal to the optical transceiver. The processing continues by converting the management data transceived with the internal modules between the generic data format and a 2nd data format (e.g., I2C). The processing continues by arbitrating access to a shared memory, which stores the management data in the generic format, between requests from internal modules via the second controller and requests from external modules via the first controller.

Abstract: A method and apparatus that includes processing for recovering data that was transported utilizing multiple data transport protocols, where such processing begins by receiving formatted data and decoding the formatted data in accordance with a second data transport protocol. The decoding recaptures a first formatted data and a first data transport identifier. The processing then continues by decoding the first formatted data in accordance with a first data transport protocol based on the first data transport identifier. For example, if the first data transport protocol is one of the IrDA data transport protocols and the second data transport protocol is the USB data transport protocol, the decoding of the formatted data is to recapture the data that is formatted in accordance with the IrDA protocol, where the first transport identifier includes information that identifies the start of IrDA formatted data and its length. It turn, by decoding the IrDA formatted data, the original data is recaptured.

Abstract: A differential latch includes a sample transistor section, a hold transistor section, a 1st gating circuit and a 2nd gating circuit. The sample transistor section is operably coupled to sample, when coupled to a supply voltage (e.g., VDD and VSS) a differential input signal. The hold transistor section is operably coupled to latch, when coupled to the supply voltage, the sampled differential input to produce a latched differential signal. The 1st gating circuit is operable to couple the sampled transistor section to the supply voltage in accordance with a 1st clocking logic operation and a 2nd clocking logic operation. The 2nd gating circuit is operable to couple the hold transistor section to the supply voltage in accordance with a 3rd clocking logic operation and a 4th clocking logic operation.

Abstract: A radio includes a self-calibrating transmitter that uses a portion of a receiver section to perform self-calibration. Accordingly, the radio includes a transmitter section, mixer, analog receiver section, calibration switch module, digital receiver section, calibration determination module, and calibration execution module. The transmitter section produces a modulated RF signal from base-band signal and a transmitter local oscillation. The mixer mixes the modulated RF signal with the transmitter local oscillation to produce a base-band representation of the modulated RF signal. In calibration mode, the calibration switch module provides the base-band representation to the receiver section, which processes the representation to produce a 2nd base-band digital signal. The calibration determination module interprets frequency components of the 2nd base-band digital signal to produce a calibration signal that compensates for imbalances within the transmitter.

Abstract: An integrated circuit includes electrical components that include one or more electrical elements on one or more dielectric layers. The electrical element has a geometric shape that exceeds prescribed integrated circuit manufacturing limits in at least one dimension. To achieve compliance with foundry rules, the electrical element is fabricated to include a non-conducting region that negligibly effects the electrical characteristics. The non-conducting region includes a hole, a series of holes, a slot and/or a series of slots spaced within the electrical element at dimensions that are less than the integrated circuit manufacturing limits.

Abstract: A multi-function interface includes a digital interface module, a configurable driver module, and a configurable output impedance module. The digital interface module is operably coupled to pass a 1st type of input signal when the interface is in a 1st mode and operably coupled to pass a 2nd type of input signal when the interface is in a 2nd mode. The configurable driver module is operably coupled to amplify the 1st type of input signal when the interface is in the 1st mode and to amplify the 2nd type of input signal when the interface is in the 2nd mode. The configurable output impedance module is coupled to the configurable driver module to provide a 1st output impedance of the interface when the interface is in the 1st mode and to provide a 2nd output impedance when the interface is in the 2nd mode.

Abstract: A high Q on-chip inductor includes a primary winding and an auxiliary winding that is coupled to receive a proportionally opposite representation of an input of the primary winding. Further, the auxiliary winding has an admittance that is greater than the admittance of the primary winding thereby yielding an asymmetry in the admittances. As such, a push/pull mechanism is obtained in a 2-port system (e.g., 1st and 2nd nodes of the primary winding) that produces a large Q factor for an on-chip inductor.

Abstract: An integrated low noise amplifier includes an on-chip balun, a line impedance matching circuit and an on-chip differential amplifier. The on-chip balun is operably coupled to convert a single ended signal into a differential signal. The line impedance matching circuit is operably coupled to the primary of the on-chip balun to provide impedance matching for a line carrying the single ended signal. The on-chip differential amplifier is operably coupled to amplify the differential signal and is impedance matched to the secondary of the on-chip balun.

Abstract: A transformer balun is obtained that is symmetrical in structure, provides high current, or high voltage, amplification and has high coupling coefficients while maintaining minimal overall size. The balun structure includes primary and secondary metal windings at separate layer interfaces. The primary and secondary metal windings are symmetrical and can have any number of turns, which is only limited by integrated circuit area and capacitance. Accordingly, the primary and secondary windings may be on as many layers as needed. Further, the primary and/or secondary may include a center tap ground, which enables the winding to be used as a differential port.

Abstract: A programmable mixer includes a 1st mixing stage, a 2nd mixing stage, a coupling element, and a compensation module. The 1st mixing stage is operably coupled to mix one leg of a differential input signal with a differential local oscillation. The 2nd mixing stage is operably coupled to mix the other leg of the differential input with the differential local oscillation. The coupling element couples the 1st and 2nd mixing stages together. The compensation module is operably coupled to the 1st mixing stage and/or the 2nd mixing stage to modify the operational characteristics (e.g., current, impedance, gain, et cetera) of the 1st and/or 2nd mixing stages based on a control signal.

Abstract: A phase locked loop includes a difference detector, a loop filter, a controlled oscillation module, and a frequency translation module. The difference detector is operably coupled to determine a difference signal based on phase and/or frequency differences between a feedback oscillation and a reference oscillation. The loop filter is operably coupled to generate a control signal from the difference signal. The controlled oscillation module is operably coupled to produce, in accordance with an adjustable operating parameter, an output oscillation based on the controlled signal. The adjustable operating parameter is set based on desired operating conditions of the phase locked loop such that false locking of the phase locked loop is substantially avoided. The frequency translation module is operably coupled to produce the feedback oscillation from the output oscillation based on a frequency translation rate.

Abstract: Interconnecting logic provides connectivity of an embedded fixed logic circuit, or circuits, with programmable logic fabric of a programmable gate array such that the fixed logic circuit functions as an extension of the programmable logic fabric. The interconnecting logic includes interconnecting tiles and may further include interfacing logic. The interconnecting tiles provide selective connectivity between inputs and/or outputs of the fixed logic circuit and the interconnects of the programmable logic fabric. The interfacing logic, when included, provides logic circuitry that conditions data transfers between the fixed logic circuit and the programmable logic fabric.

Abstract: A digital-to-analog converter includes a plurality of current sources, a differential amplifier, and a plurality of switching modules. The plurality of switching modules is operably coupled to the plurality of current sources and the digital amplifier module provides the analog output for the digital-to-analog converter. Each of the plurality of switching modules has a corresponding current source of the plurality of current sources, where a 1st set of the plurality of switching modules couples the corresponding current sources to the differential amplifier module in a 1st manner based on a digital input value and a 2nd set of the plurality of switching modules couples the corresponding current sources to the differential amplifier in a 2nd manner based on the digital input values such that, over time, errors introduced by the coupling in the 1st manner substantially compensates for errors introduced by the coupling in the 2nd manner.

Abstract: An improved switch capacitor circuit includes a capacitor, a 1st voltage reference module, a 2nd voltage reference module, and a plurality of switching elements. The capacitor is operably coupled via the plurality of switching elements to sample an input signal during a 1st interval of a sampling period and during a 2nd interval of the sampling period to provide a representation of the input signal. The 2nd reference module produces a 2nd reference voltage that is representative of the common mode of the supply (e.g. VDD and VSS). The 1st voltage reference module produces a 1st reference voltage that is representative of the common mode of the analog input signal. As such, the capacitor is charged during the 1st interval based on the 1st reference voltage and discharged during the 2nd interval based on the 2nd reference voltage.