Abstract: A DRAM memory array is disclosed that uses a current limiting circuit employing current feedback to clamp the current flow to reduced levels than were previously possible. The current limiting circuit comprises a long length, depletion mode transistor that has its gate voltage reduced when row-to-column shorts exist to limit the bleed current. An alternative embodiment uses a P-channel FET in series with the depletion mode transistor and has its gate tied to a negative supply and passes current until both digit lines approach approximately 0.3 Volts.

Abstract: The formation of routing traces on an external surface of a semiconductor device, such as a flip-chip, which has a plurality of ball or bump sites patterned in specific locations, wherein the ball or bump sites are in electrical communication with external communication traces which are used to route signals from the flip-chip integrated circuitry. Such external communication traces generally result in unused space on the exterior surface of the flip-chip. This unused space can be utilized for forming routing traces to connect portions of the internal circuitry of the flip-chip rather than forming such routing traces internally, for forming routing traces to connect two or more semiconductor dice, or for forming routing traces for use as repair mechanisms.

Abstract: A battery mounting contact consists of a substrate having a battery cavity for housing a battery therein. A first contact is attached to a first surface of the substrate and extends over the battery cavity substantially planarly adjacent to the substrate first surface. A second contact extends over the battery cavity substantially planarly adjacent to a second surface of the substrate. The battery, disposed within the battery cavity, makes electrical contact by its anode with the first contact and by its cathode with the second contact, or vis versa. The battery mounting contact significantly reduces the thickness of a battery powered device.

Abstract: A method of manufacturing a drill bit or other drilling-related structure used for drilling into subterranean formations is herein disclosed where a blank is formed by placing a ferrous metal powder such as steel into a mold, sintering the ferrous metal powder to form a preformed blank, packing an abrasion- and erosion-resistant material such as tungsten carbide powder around the preformed blank, and infiltrating the preformed blank and tungsten carbide with a common binder such as a copper-based binder. For some materials, during sintering, the preformed blank may shrink in size relative to the mold enough to provide space between the mold and the preformed blank for a layer of abrasion- and erosion-resistant material. With other materials, a separate blank mold may be used to form the sintered blank which can then be inserted into the mold for infiltration.

Abstract: A frame is formed of side walls that are extruded from vinyl. The side walls have interior channels. The side walls may be formed to effect a female-male connection between the ends of two adjoining side walls. Alternatively a locking member is provided that is sized to frictionally engage a selected channel. The side walls have a concrete retention fin positioned to extend away from the outer wall of the side wall to interconnect with the concrete as the and after the concrete cures. The frame may be formed into door jambs, doors, and the like. The frame may also be a window buck that may be formed into selected geometric shapes. Window bucks of different dimensions may be assembled on site by sawing.

Abstract: The present invention relates to circuit defect detection, classification, and review in the wafer stage of the integrated circuit semiconductor device manufacturing process. The method of processing integrated circuit semiconductor dice on a wafer in a manufacturing process for dice comprising the steps of visually inspecting said dice on said wafer to determine defects thereon, summarizing the number, types, and ranges of sizes of the defects of said dice on said wafer, and determining if said wafer is acceptable to proceed in said manufacturing process.

Abstract: A method and apparatus for measuring the surface temperatures of wire-bonded semiconductors and the like for preparing thermal maps include a conventional ultrasonic wire bonding machine adapted for mounting a fluorescence-decay temperature sensor in the capillary holder. A trigger box circuit is provided to trigger a temperature measurement based on initiation of an electrical voltage signal from the ultrasonic bonding controller. A computer is provided for coordinating the stage control and temperature measurements, and for collating and plotting the temperature, time and location indications as thermal maps and other displayed/printed correlations.

Abstract: A semiconductor package for vertically surface mounting to a printed circuit board having retention apparatus for holding the package thereto.

Abstract: A condensed memory matrix is fabricated by conductively connecting the attachment bumps of a substrate with the attachment bumps of a wafer of DRAM chips and physically bonding the juxtaposed surfaces of the substrate and the wafer with a dielectric curable resin. An array of heat fins is bonded to the inactive surface of the wafer by a thermally conductive curable resin.

Abstract: A multi-leadframe die assembly is disclosed including a die bonded to a die paddle. A second lead frame including leads is superimposed and bonded onto the first lead frame. Also disclosed is a method for fabricating the multi part lead frame assembly which utilizes equipment designed for single lead frame processing. If desired, the materials for the multi part lead frame may be dissimilar.

Abstract: A stackable fine ball grid array (FBGA) package is disclosed that allows the stacking of one array upon another. This stackable FBGA package is configured such that conductive elements are placed along the outside perimeter of an integrated circuit (IC) device mounted to the FBGA. The conductive elements also are of sufficient size so that they extend beyond the bottom or top surface of the IC device, including the wiring interconnect and encapsulate material, as the conductive elements make contact with the FBGA positioned below or above to form a stack. The IC device, such as a memory chip, is mounted upon a first surface of a printed circuit board substrate forming part of the FBGA. Lead wires are used to attach the IC device to the printed board substrate and encapsulant is used to contain the IC devices and wires within and below the matrix and profile of the conductive elements. Additionally, certain pins on the FBGA in the stack require an isolated connection to the PC board.

Abstract: An oximetry sensor comprising a foam wrap member including a fastener, back film mounting member, LED assembly and photodiode connected to a cable, support rings for the LED assembly and photodiode, window film for the LED assembly and photodiode, and a top liner.

Abstract: An inventive electronic device, such as a multi-chip module (MCM), a Single In-line Memory Module (SIMM), or a Dual In-line Memory Module (DIMM), includes a base, such as a printed circuit board, having a surface on which flip-chip pads and wire-bondable pads are provided. The flip-chip pads define an area on the surface of the base at least partially bounded by the wire-bondable pads. A first integrated circuit (IC) die is flip-chip bonded to the flip-chip pads, and a second IC die is back-side attached to the first IC die and then wire-bonded to the wire-bondable pads. As a result, the flip-chip mounted first IC die is stacked with the second IC die in a simple, novel manner.

Abstract: A device for overload protection and for braking a machine part driven by a motor (2), in particular, a tool driven by a cam gear in a stamping and/or bending machine, comprises a module (3), an overload clutch (4) disengaging after exceeding a torque threshold, and a freewheel (6) which, during the braking of the drive shaft (1) blocks in the direction of drive, each being arranged on the drive shaft (1) behind one another in the drive line extending from the motor (2) to the machine part.

Abstract: A wire-bonding machine includes a heat block for supporting a lead frame during wire-bonding. A clamp mechanism in the machine clamps leads of the lead frame during wire-bonding by fixedly holding sets of the leads against the heat block one set at a time. A wire-bonding tool wire-bonds leads clamped by the clamp mechanism to bond pads on an integrated circuit die. By clamping leads of the lead frame in separate sets, the machine provides improved clamping for lead frames with leads requiring clamping in different planes.

Abstract: A semiconductor die assembly comprising a semiconductor die with bond pads, a plurality of leads which extends across the semiconductor die and terminate over its respective bond pads, and an alpha barrier preferably positioned between the leads and the semiconductor die. Electrical connection is made between the leads and their respective bond pads by a strip of anisotropically conductive elastomeric material, preferably a multi-layer laminate consisting of alternating parallel sheets of a conductive foil and an insulating elastomer wherein the laminate layers are oriented perpendicular to both the bond pad and the lead, positioned between the leads and the bond pads. A burn-in die according to the present invention is also disclosed.

Abstract: Techniques for melting and forming aerosols from solid CIPC are disclosed. Solid CIPC in block form is convenient to ship and to handle. Solid CIPC in block form appears to have a consistency of solid paraffin wax. Solid CIPC is melted by controlled techniques to form a substantially pure liquid stream of CIPC. The molten or liquid stream of CIPC is converted to an aerosol of CIPC either by a pressurized, hot air stream or by a combustion gas stream.

Abstract: A method of forming an isolation structure comprising forming n-type areas and/or p-type areas implanted respectively therein on a first surface of the substrate. A pad oxide film is grown on the substrate first surface covering the p-wells and/or n-wells. A diffusion barrier(s) is deposited on the substrate first surface and a substrate second surface to form an encapsulated structure. The encapsulated structure is annealed to activate the n-type and/or p-type areas. A mask material is applied over the diffusion barrier on the substrate first surface to define active device areas and a dry etch process is used to etch away the unmasked portions of the diffusion barrier. The mask material is stripped and a field oxide is grown on the substrate first surface. A portion of the field oxide and all of the diffusion barrier is removed, resulting in active areas surrounded by a field isolation structure.

Abstract: A buried contact is formed in a substrate implantation of phosphorous or arsenic through a window cut into the insulating silicon oxide layer and a superimposed thin silicon layer. The photoresist used to etch the window is cut back a limited amount prior to implantation. The peripheral margin of the buried contact implanted through the exposed part of the thin layer of silicon lowers the threshold voltage of any parasitic MOS device which may be created between the buried contact and the remote N+source or drain structure.