Abstract: Systems and methods for managing email are provided. Some of the email may be encrypted using identity-based-encryption (IBE) techniques. When an incoming IBE-encrypted message for a recipient in an organization is received by a gateway at the organization, the gateway may request an IBE private key from an IBE private key generator. The IBE private key generator may generate the requested IBE private key for the gateway. The gateway may use an IBE decryption engine to decrypt the incoming message. The decrypted message can be scanned for viruses and spam and delivered to the recipient. Outgoing email messages can also be processed. If indicated by message attributes or information provided by a message sender, an outgoing message can be encrypted using an IBE encryption engine and the IBE public key of a desired recipient.

Abstract: Handheld electronic devices are provided that contain wireless communications circuitry having at least one antenna. The antenna may have a planar ground element and a planar resonating element. The planar ground element may have a rectangular shape that matches a rectangular housing shape for a handheld electronic device. A dielectric-filled slot may be formed in one end of the planar ground element. The planar resonating element may be located above the slot. The antenna may be a hybrid antenna that contains both a slot antenna structure formed from the slot and a planar inverted-F structure formed from the planar resonating element and the planar ground element. The antenna may be fed using a single transmission line or two transmission lines. With two transmission lines, one transmission line may be associated with the slot antenna structure and one transmission line may be associated with the planar inverted-F antenna structure.

Abstract: Image sensors and color filter arrays for in-pixel charge summing and interlaced readout modes may be provided. An image sensor that supports charge summing and interlaced readout modes may include an array of pixels with pairs of adjacent green, red, and blue light-sensitive pixels. An image sensor may implement an in-pixel charge summing readout mode in which charges from pairs of pixels are summed onto a common node and then read out from the common node. An image sensor may implement an interlaced readout mode in which image data is read out from alternating rows of the image sensor. An image sensor may use a shared readout scheme in which a group of four pixels is formed from two pairs of commonly-colored pixels. The four pixels may share circuitry such as a reset transistor, a buffer transistor, and a row select transistor and may connect to a single readout line.

Abstract: Connectors for cables such as a 30-pin connector are provided. The connectors may have thermal protection circuits and may carry a power supply voltage and a ground voltage. The thermal protection circuits may disable the power supply voltage when the temperature of the connector exceeds a threshold value. The connectors may have structures that encourage any dendritic failure to occur in a preferred location.

Abstract: Printed circuit boards are provided with embedded components. The embedded components may be mounted within recesses in the surface of a printed circuit board substrate. The printed circuit board substrate may have grooves and buried channels in which wires may be mounted. Recesses may be provided with solder pads to which the wires may be soldered or attached with conductive adhesive. An integrated switch may be provided in an opening within a printed circuit board substrate. The integrated switch may have a dome switch member that is mounted within the opening. A cover member for the switch may be formed from a flexible layer that covers the dome switch member. Terminals for the integrated switch may be formed from conductive structures in an interior printed circuit board layer. Interconnects may be used to electrically connect embedded components such as switches, integrated circuits, solder pads for wires, and other devices.

Abstract: A verifiable duplex multiplier circuit is provided. In one mode, the circuitry of the duplex multiplier functions as an N-bit×N-bit multiplier. In another mode, the circuitry of the duplex multiplier operates as dual N/2-bit×N/2-bit multipliers. Because the same circuitry can be used to serve as both an N×N multiplier and as dual N/2×N/2 multipliers, integrated circuit resources are conserved. The duplex multiplier circuitry uses an architecture that can be automatically synthesized using a logic synthesis tool. Verification operations can be performed using logic-equivalency error checking tools. Exhaustive verification is possible using this approach, even when relatively large duplex multipliers (e.g., duplex multipliers with N values of 16 or more) are used.

Abstract: Electrical devices may be tested using test equipment. A device may have an associated cable with a connector. The test equipment may have an associated cable with a connector. An adapter may have a pair of connectors. One of the adapter connectors may be connected to the connector of the cable associated with the device and the other of the adapter connectors may be connected to the connector of the cable that is associated with the tester. A retention clip may be attached to a groove in the adapter. Flexible members in the clip may each grasp an opposing side of the adapter within the groove. A retention member in the clip may bear against the connector on the cable that is associated with the device to hold the connectors for the device cable and the adapter together.

Abstract: Connectors for electronic devices are provided with embedded antennas. The connectors may be 30-pin connectors. A 30-pin connector may have a conductive shell structure that defines a cavity and a planar dielectric member that extends into the cavity and that has contact pins. An antenna may be formed from an antenna resonating element on the planar dielectric member and an antenna ground formed from the conductive shell structure. An antenna may be formed from a slot in the conductive shell. The antenna and the pins may be electrically coupled to an electronic device using a cable.

Abstract: Image sensors are provided for electronic imaging devices. An image sensor can be formed from an array of image pixels. Bragg-type multilayer interference filters can be formed for the image sensor using dielectric layers with alternating high and low indices of refraction. The multilayer interference filters can be configured to form band-pass filters of desired colors and infrared-blocking filters. Dielectric layers with non-flat bulk absorption properties may be used to tune the absorption of the filters. The interference filters may be provided in a uniform pattern so that an image sensor exhibits a monochrome response or may be arranged in a multicolor color filter array pattern such as a Bayer pattern.

Abstract: Circuitry for portable electronic devices is provided. The circuitry may include wireless communications circuitry and storage and processing circuitry. The wireless communications circuitry may include an antenna and a radio-frequency power amplifier with an adjustable gain mode. The radio-frequency power amplifier may amplify radio-frequency signals to a given output power. The circuitry may include an adjustable power supply circuit that supplies an adjustable power supply voltage to the power amplifier circuitry. The circuitry may also include a transceiver that produce radio-frequency signals at a specified input power to the power amplifier circuitry. The storage and processing circuitry may be used in storing calibration data. The calibration data may specify adjustments to be made to the input power to the radio-frequency power amplifier, the gain mode setting of the power amplifier, and the power supply voltage for the power amplifier to optimize performance while minimizing power consumption.

Abstract: Wireless portable electronic devices such as laptop computers are provided with antennas. An antenna may be provided within a clutch barrel in a laptop computer. The clutch barrel may have a dielectric cover. Antenna elements may be mounted within the clutch barrel cover on an antenna support structure. There may be two or more antenna elements mounted to the antenna support structure. These antenna elements may be of different types. A first antenna element for the clutch barrel antenna may be formed from a dual band antenna element having a closed slot and an open slot. A second antenna element for the clutch barrel antenna may be formed from a dual band antenna element of a hybrid type having a planar resonating element arm and a slot resonating element. Flex circuit structures may be used in implanting the first and second antenna elements for the clutch barrel antenna.

Abstract: An imaging system may include an imager with pixels and with reset lines that can be selectively deactivated and floated. When the reset lines are deactivated and floated, the reset lines may be connected to floating diffusion nodes in the pixels to increase the capacitance of the floating diffusion nodes. The reset lines may have parasitic capacitances that are used to supplement the capacitances of the floating diffusion nodes, when the reset lines are connected to the floating diffusion nodes. The imager may be used to capture high dynamic range images by simultaneously capturing a first image with a long integration time and a second image with a short integration time. The first and second images may be combined into a high dynamic range image.

Abstract: Logo antennas are provided for electronic devices such as portable computers. An electronic device may have a housing with conductive housing walls. A logo antenna may be formed from an antenna resonating element such as a patch antenna resonating element, a monopole antenna resonating element, or other antenna resonating element structure. A conductive cavity may be placed behind the antenna resonating element. A dielectric antenna window that serves as a logo may be used to cover the antenna resonating element. The dielectric antenna window may be mounted in an opening in the conductive housing walls. A positive antenna feed terminal may be coupled to the antenna resonating element. A ground antenna feed terminal may be coupled to the cavity and portions of the conductive housing walls. The dielectric antenna window may be shaped in the form of a logo.

Abstract: Systems and methods for supporting symmetric-bilinear-map and asymmetric-bilinear-map identity-based-encryption (IBE) key exchange and encryption schemes are provided. IBE key exchange schemes use an IBE encapsulation engine to produce a secret key and an encapsulated version of the secret key. An IBE unencapsulation engine is used to unencapsulate the encapsulated key. IBE encryption schemes use an IBE encryption engine to produce ciphertext from plaintext. An IBE decryption engine is used to decrypt the ciphertext to reveal the plaintext. The IBE unencapsulation engine and decryption engines use bilinear maps. The IBE encapsulation and encryption engines perform group multiplication operations without using bilinear maps, improving efficiency. IBE private keys for use in decryption and unencapsulation operations may be generated using a distributed key arrangement in which each IBE private key is assembled from private key shares.

Abstract: A cavity antenna for an electronic device such as a portable computer is provided. The antenna may be formed from a conductive cavity and an antenna probe that serves as an antenna feed. The conductive cavity may have the shape of a folded rectangular cavity. A dielectric support structure may be used in forming the antenna cavity. A fin may protrude from one end of the dielectric support structure. The antenna probe may be formed from conductive structures mounted on the fin. An inverted-F antenna configuration or other antenna configuration may be used in forming the antenna probe. The electronic device may have a housing with conductive walls. When the cavity antenna mounted within an electronic device, a planar rectangular end face of the fin may protrude through a thin rectangular opening in the conductive walls to allow the antenna to operate without being blocked by the housing.

Abstract: Integrated circuits with phase-locked loops are provided. Phase-locked loops may include an oscillator, a phase-frequency detector, a charge pump, a loop filter, a voltage-controlled oscillator, and a programmable divider. The voltage-controlled oscillator may include multiple inductors, an oscillator circuit, and a buffer circuit. A selected one of the multiple inductors may be actively connected to the oscillator circuit. The voltage-controlled oscillators may have multiple oscillator circuits. Each oscillator circuit may be connected to a respective inductor, may include a varactor, and may be powered by a respective voltage regulator. Each oscillator circuit may be coupled to a respective input transistor pair in the buffer circuit through associated coupling capacitors. A selected one of the oscillator circuits may be turned on during normal operation by supplying a high voltage to the selected one of the oscillator circuit and by supply a ground voltage to the remaining oscillator circuits.

Abstract: A system is provided that uses cryptographic techniques to support secure messaging between senders and recipients. A sender may encrypt a message for a recipient using the recipient's public key. The sender may send the encrypted message to the message address of a given recipient. A server may be used to decrypt the encrypted message for the recipient, so that the recipient need not install a decryption engine on the recipient's equipment.

Abstract: Integrated circuits with data communications circuitry are provided. The data communications circuitry on an integrated circuit may receive data that was transmitted from another integrated circuit at a data rate. The data communications circuitry may include oversampling circuitry that oversamples the data to produce an oversampled version of the data at an oversampled data rate. Downsampling circuitry in the data communications circuitry may be used to downsample the oversampled data. The downsampling circuitry may include cascaded groups of registers that store the oversampled data. The outputs of each of the groups of registers may be combined to form a combined parallel output. A downsampling control circuit may have a multiplexer that selects a subset of the signals from the combined parallel output in response to control signals from a transition detector. A middle bit detector may extract a bit value from the selected subset to use as the downsampled output.

Abstract: Integrated circuits with delay circuitry are provided. Delay circuitry may receive a clock signal and generate a corresponding delayed clock signal. The delayed clock signal generated using the delay circuitry may exhibit reduced duty cycle distortion in comparison to conventional systems. The delay circuitry may include a pulse generation circuit, a delay circuit, and a latching circuit. The pulse generation circuit may generate pulses in response to detecting rising edges or falling edges at its input. The pulses may propagate through the delay circuit. The latching circuit may generate (reconstruct) a delayed version of the clock signal in response to receiving the pulses at its control input. The delay circuitry may be used in duty cycle distortion correction circuitry, delay-locked loops, and other control circuitry.

Abstract: Memory elements are provided that exhibit immunity to soft error upsets. The memory elements may have cross-coupled inverters. The inverters may be implemented using programmable Schmitt triggers. The memory elements may be locked and unlocked by providing appropriate power supply voltages to the Schmitt trigger. The memory elements may each have four inverter-like transistor pairs that form a bistable element, at least one address transistor, and at least one write enable transistor. The write enable transistor may bridge two of the four nodes. The memory elements may be locked and unlocked by turning the write enable transistor on and off. When a memory element is unlocked, the memory element is less resistant to changes in state, thereby facilitating write operations. When the memory element is locked, the memory element may exhibit enhanced immunity to soft error upsets.